commit 00a6e7e9cc488d819501b4b28ea01745faa0ba77
parent 8232199844c35a09ed2bde578493b4a0d7fd42c6
Author: RahulSannapureddy <rahul.sannapureddy@gmail.com>
Date: Tue, 21 Apr 2026 14:51:25 +0530
Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 2: Core logic)
Diffstat:
5 files changed, 230 insertions(+), 0 deletions(-)
diff --git a/output-pii/nfa_3.v b/output-pii/nfa_3.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 3
+module nfa_3 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output wire match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [11:0] state_reg;
+ wire [11:0] next_state;
+
+ assign next_state[0] = 1'b1;
+ assign next_state[1] = (state_reg[0] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[2] = (state_reg[1] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[3] = (state_reg[2] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[4] = (state_reg[3] && (char_in == 8'd45));
+ assign next_state[5] = (state_reg[4] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[6] = (state_reg[5] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[7] = (state_reg[6] && (char_in == 8'd45));
+ assign next_state[8] = (state_reg[7] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[9] = (state_reg[8] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[10] = (state_reg[9] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[11] = (state_reg[10] && (char_in >= 8'd48) && (char_in <= 8'd57));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted immediately on accept state (combinational)
+ assign match = state_reg[11];
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[11:1];
+
+endmodule
diff --git a/output-pii/nfa_4.v b/output-pii/nfa_4.v
@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 4
+module nfa_4 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output wire match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [16:0] state_reg;
+ wire [16:0] next_state;
+
+ assign next_state[0] = 1'b1;
+ assign next_state[1] = (state_reg[0] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[2] = (state_reg[1] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[3] = (state_reg[2] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[4] = (state_reg[3] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[5] = (state_reg[4] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[6] = (state_reg[5] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[7] = (state_reg[6] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[8] = (state_reg[7] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[9] = (state_reg[8] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[10] = (state_reg[9] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[11] = (state_reg[10] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[12] = (state_reg[11] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[13] = (state_reg[12] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[14] = (state_reg[13] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[15] = (state_reg[14] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[16] = (state_reg[15] && (char_in >= 8'd48) && (char_in <= 8'd57));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted immediately on accept state (combinational)
+ assign match = state_reg[16];
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[16:1];
+
+endmodule
diff --git a/output-pii/nfa_5.v b/output-pii/nfa_5.v
@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 5
+module nfa_5 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output wire match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [7:0] state_reg;
+ wire [7:0] next_state;
+
+ assign next_state[0] = 1'b1;
+ assign next_state[1] = (state_reg[0] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[1] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[2] = (state_reg[1] && (char_in == 8'd46));
+ assign next_state[3] = (state_reg[2] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[3] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[4] = (state_reg[3] && (char_in == 8'd46));
+ assign next_state[5] = (state_reg[4] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[5] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[6] = (state_reg[5] && (char_in == 8'd46));
+ assign next_state[7] = (state_reg[6] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[7] && (char_in >= 8'd48) && (char_in <= 8'd57));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted immediately on accept state (combinational)
+ assign match = state_reg[7];
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[7:1];
+
+endmodule
diff --git a/output-pii/nfa_6.v b/output-pii/nfa_6.v
@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 6
+module nfa_6 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output wire match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [10:0] state_reg;
+ wire [10:0] next_state;
+
+ assign next_state[0] = 1'b1;
+ assign next_state[1] = (state_reg[0] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[2] = (state_reg[1] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[3] = (state_reg[2] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[4] = (state_reg[3] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[5] = (state_reg[4] && (char_in == 8'd45));
+ assign next_state[6] = (state_reg[5] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[7] = (state_reg[6] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[8] = (state_reg[7] && (char_in == 8'd45));
+ assign next_state[9] = (state_reg[8] && (char_in >= 8'd48) && (char_in <= 8'd57));
+ assign next_state[10] = (state_reg[9] && (char_in >= 8'd48) && (char_in <= 8'd57));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted immediately on accept state (combinational)
+ assign match = state_reg[10];
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[10:1];
+
+endmodule
diff --git a/output-pii/top.v b/output-pii/top.v
@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+
+module top (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output wire [6:0] match_bus,
+ output wire [6:0] active_bus
+);
+
+ nfa_0 inst_0 (
+ .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[0]), .active(active_bus[0])
+ );
+
+ nfa_1 inst_1 (
+ .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[1]), .active(active_bus[1])
+ );
+
+ nfa_2 inst_2 (
+ .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[2]), .active(active_bus[2])
+ );
+
+ nfa_3 inst_3 (
+ .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[3]), .active(active_bus[3])
+ );
+
+ nfa_4 inst_4 (
+ .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[4]), .active(active_bus[4])
+ );
+
+ nfa_5 inst_5 (
+ .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[5]), .active(active_bus[5])
+ );
+
+ nfa_6 inst_6 (
+ .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[6]), .active(active_bus[6])
+ );
+
+endmodule