xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3// NFA for regex index 4
 4module nfa_4 (
 5    input  wire       clk,
 6    input  wire       en,
 7    input  wire       rst,
 8    input  wire       start,
 9    input  wire       end_of_str,
10    input  wire [7:0] char_in,
11    output wire       match,
12    output wire       active
13);
14
15    // One-hot state register
16    reg [16:0] state_reg;
17    wire [16:0] next_state;
18
19    assign next_state[0] = 1'b1;
20    assign next_state[1] = (state_reg[0] && (char_in >= 8'd48) && (char_in <= 8'd57));
21    assign next_state[2] = (state_reg[1] && (char_in >= 8'd48) && (char_in <= 8'd57));
22    assign next_state[3] = (state_reg[2] && (char_in >= 8'd48) && (char_in <= 8'd57));
23    assign next_state[4] = (state_reg[3] && (char_in >= 8'd48) && (char_in <= 8'd57));
24    assign next_state[5] = (state_reg[4] && (char_in >= 8'd48) && (char_in <= 8'd57));
25    assign next_state[6] = (state_reg[5] && (char_in >= 8'd48) && (char_in <= 8'd57));
26    assign next_state[7] = (state_reg[6] && (char_in >= 8'd48) && (char_in <= 8'd57));
27    assign next_state[8] = (state_reg[7] && (char_in >= 8'd48) && (char_in <= 8'd57));
28    assign next_state[9] = (state_reg[8] && (char_in >= 8'd48) && (char_in <= 8'd57));
29    assign next_state[10] = (state_reg[9] && (char_in >= 8'd48) && (char_in <= 8'd57));
30    assign next_state[11] = (state_reg[10] && (char_in >= 8'd48) && (char_in <= 8'd57));
31    assign next_state[12] = (state_reg[11] && (char_in >= 8'd48) && (char_in <= 8'd57));
32    assign next_state[13] = (state_reg[12] && (char_in >= 8'd48) && (char_in <= 8'd57));
33    assign next_state[14] = (state_reg[13] && (char_in >= 8'd48) && (char_in <= 8'd57));
34    assign next_state[15] = (state_reg[14] && (char_in >= 8'd48) && (char_in <= 8'd57));
35    assign next_state[16] = (state_reg[15] && (char_in >= 8'd48) && (char_in <= 8'd57));
36
37    always @(posedge clk) begin
38        if (rst || start) begin
39            // Reset to start state (one-hot)
40            state_reg <= 1 << 0;
41        end else if (en) begin
42            state_reg <= next_state;
43        end
44    end
45
46    // Match logic: asserted immediately on accept state (combinational)
47    assign match = state_reg[16];
48
49    // Active logic: high if any state other than state 0 is active
50    assign active = |state_reg[16:1];
51
52endmodule