xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3// NFA for regex index 5
 4module nfa_5 (
 5    input  wire       clk,
 6    input  wire       en,
 7    input  wire       rst,
 8    input  wire       start,
 9    input  wire       end_of_str,
10    input  wire [7:0] char_in,
11    output wire       match,
12    output wire       active
13);
14
15    // One-hot state register
16    reg [7:0] state_reg;
17    wire [7:0] next_state;
18
19    assign next_state[0] = 1'b1;
20    assign next_state[1] = (state_reg[0] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[1] && (char_in >= 8'd48) && (char_in <= 8'd57));
21    assign next_state[2] = (state_reg[1] && (char_in == 8'd46));
22    assign next_state[3] = (state_reg[2] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[3] && (char_in >= 8'd48) && (char_in <= 8'd57));
23    assign next_state[4] = (state_reg[3] && (char_in == 8'd46));
24    assign next_state[5] = (state_reg[4] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[5] && (char_in >= 8'd48) && (char_in <= 8'd57));
25    assign next_state[6] = (state_reg[5] && (char_in == 8'd46));
26    assign next_state[7] = (state_reg[6] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[7] && (char_in >= 8'd48) && (char_in <= 8'd57));
27
28    always @(posedge clk) begin
29        if (rst || start) begin
30            // Reset to start state (one-hot)
31            state_reg <= 1 << 0;
32        end else if (en) begin
33            state_reg <= next_state;
34        end
35    end
36
37    // Match logic: asserted immediately on accept state (combinational)
38    assign match = state_reg[7];
39
40    // Active logic: high if any state other than state 0 is active
41    assign active = |state_reg[7:1];
42
43endmodule