xiiregexbuilder

FPGA-Accelerated Regular Expression Matching Engine
commit 95ad58a8359cbd2ad7cb090aba50c641410c0418
parent 10295686a022feddee6768c9b2a04d20e4e8d9c0
Author: RahulSannapureddy <rahul.sannapureddy@gmail.com>
Date:   Wed, 22 Apr 2026 19:42:51 +0530

Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 3: Finalizing)

Diffstat:
Apii/demo_input.txt | 80+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Apii/pii_regexes.txt | 15+++++++++++++++
Ascripts/synth_pii.tcl | 34++++++++++++++++++++++++++++++++++
Mtui/engine.py | 18+++++++++---------
Atui/pii_demo.py | 81+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Atui/requirements.txt | 3+++
6 files changed, 222 insertions(+), 9 deletions(-)

diff --git a/pii/demo_input.txt b/pii/demo_input.txt @@ -0,0 +1,80 @@ +INCIDENT LOG - DATA PRIVACY AUDIT +==================================== + +[2026-04-23] INFO: System initialization complete. Scanning stream for sensitive data. +[2026-04-23] USER: Alice (alice.smith@example.com) logged in from IP 10.0.0.42. +[2026-04-23] TRANSACTION: Processing payment for order #8821. CC: 4111222233334444. +[2026-04-23] RECORD: Patient John Doe (SSN: 999-12-4455) visited the clinic. +[2026-04-23] SUPPORT: Received call from customer at 555-123-4567 regarding billing. +[2026-04-23] NETWORK: Potential breach detected from source 192.168.1.105. +[2026-04-23] FINANCE: Refund issued to 1111222233334444. +[2026-04-23] HR: Background check for candidate with SSN 123-44-5678 completed. +[2026-04-23] CONTACT: Reach out to tech.support@corporation.net for server 172.16.254.1. + +Customer Registry Entry #1: Robert Johnson, 5550192837, r.johnson@provider.com, IP: 8.8.8.8. +Customer Registry Entry #2: Sarah Connor, 123-456-7890, s.connor@resistance.io, SSN: 000-00-0001. +Customer Registry Entry #3: Thomas Anderson, 9998887776, neo@matrix.net, CC: 5555444433332222. +Customer Registry Entry #4: Bruce Wayne, 1112223333, batman@gotham.city, IP: 127.0.0.1. + +Employee Payroll Export: +Name: James Howlett, DOB: 1880-10-21, SSN: 001-01-0001, Phone: 9005550199. +Name: Wade Wilson, DOB: 1973-11-22, SSN: 666-00-6666, Phone: 555-555-1212. +Name: Peter Parker, DOB: 2001-08-10, SSN: 201-00-1234, Email: spider.man@queens.ny.us. + +Web Access Log Snippets: +192.168.1.1 - - [2026-04-23:10:00:00] "GET /admin/login HTTP/1.1" 200 +10.42.1.254 - - [2026-04-23:10:05:22] "POST /api/v1/auth/email=dev.user@internal.dev" 200 +172.31.0.100 - - [2026-04-23:10:10:45] "PUT /users/update/cc=4242424242424242" 403 + +Medical Database Backup: +RecordID, FullName, Identification, ContactPhone, DateOfEntry +1001, Arthur Dent, 042-00-1234, 444-555-6666, 2026-04-23 +1002, Ford Prefect, 999-99-9999, 1234567890, 2026-04-23 +1003, Tricia McMillan, 111-22-3333, 555-010-9988, 2026-04-23 + +Infrastructure Status: +Gateway 1: 10.0.0.1 (Active) +Gateway 2: 10.0.0.2 (Standby) +Monitoring Node: monitoring.admin@cluster.local +Database Cluster Primary: 10.0.5.10 +Database Cluster Replica: 10.0.5.11 + +Internal Communications: +From: accounting@firm.com +To: executive.assistant@firm.com +Subject: Quarterly SSN Verification +Please verify the following tax IDs: 555-66-7788, 444-33-2211, and 111-00-1111. +Payments were sent to Visa ending in 4111222233334444. + +Automated Alert: +Unauthorized login attempt for user admin@secure.vault.com. +Originating IP: 185.22.33.44. +Time: 2026-04-23 15:30:12. + +Legacy System Migration Data: +OLD_PHONE: 2125550198 -> NEW_PHONE: 212-555-0198 +OLD_CC: 1234123412341234 -> NEW_CC: 1234123412341234 +OLD_IP: 192.168.000.001 -> NEW_IP: 192.168.0.1 + +Testing various phone formats: +- 1234567890 (redact) +- 123-456-7890 (redact) +- 123.456.7890 (no redact) +- (123) 456-7890 (no redact) + +Testing overlapping patterns: +Email containing digits: user1234567890@site.com +IP containing SSN-like block: 123.45.67.89 +CC following an IP: 10.0.0.1 4111222233334444 + +End of Batch Data Processing. +Timestamp: 2026-04-23 23:59:59. +Status: Success. +Archive IP: 10.10.10.10 +Encryption Key ID: 5551234567890123 + +Closing stream. +Final Audit Date: 2026-04-23. +Reporting SSN: 000-00-0000. +Final verification: CC 9999888877776666. +Goodbye. diff --git a/pii/pii_regexes.txt b/pii/pii_regexes.txt @@ -0,0 +1,15 @@ +# Redaction Patterns +# Email +[a-zA-Z0-9.]+@[a-zA-Z0-9.]+\.[a-zA-Z]+ +# Phone: Standard 10-digit +[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9] +# Phone: Dashed format +[0-9][0-9][0-9]-[0-9][0-9][0-9]-[0-9][0-9][0-9][0-9] +# SSN: Standard 3-2-4 format +[0-9][0-9][0-9]-[0-9][0-9]-[0-9][0-9][0-9][0-9] +# Credit Card: 16 digits +[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9] +# IP Address: IPv4 simple +[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+ +# Date: YYYY-MM-DD +[0-9][0-9][0-9][0-9]-[0-9][0-9]-[0-9][0-9] diff --git a/scripts/synth_pii.tcl b/scripts/synth_pii.tcl @@ -0,0 +1,34 @@ +# VIVADO SYNTHESIS & BITSTREAM SCRIPT +# This script automates the flow for the PII Guard Demo + +# 1. Define target part +set part xc7a100tcsg324-1 +set outputDir ./build +file mkdir $outputDir + +# 2. Create the project in memory +create_project -in_memory -part $part + +# 3. Read Verilog Files +read_verilog [glob output/*.v] + +# 4. Read Constraints +read_xdc output/constraints.xdc + +# 5. Run Synthesis +synth_design -top top_fpga -part $part + +# 6. Run Implementation Flow +opt_design +place_design +route_design + +# 7. Generate Reports +report_utilization -file $outputDir/post_route_util.txt +report_timing_summary -file $outputDir/post_route_timing.txt + +# 8. Generate Bitstream +write_bitstream -force $outputDir/top_fpga.bit + +# 9. Cleanup and close +close_project diff --git a/tui/engine.py b/tui/engine.py @@ -14,7 +14,7 @@ Usage --port Serial port (default: auto-detect first USB-Serial) --baud Baud rate (default: 115200) --regexes Path to inputs/regexes.txt for label display (optional but - strongly recommended — falls back to "Regex 0", "Regex 1", …) + strongly recommended - falls back to "Regex 0", "Regex 1", …) Protocol ──────── @@ -24,10 +24,10 @@ Protocol Controls ──────── - Enter — send current input to FPGA - Ctrl-C / q — quit - Ctrl-L — clear input line - ? — query current counters without sending a string + Enter - send current input to FPGA + Ctrl-C / q - quit + Ctrl-L - clear input line + ? - query current counters without sending a string """ import argparse @@ -73,7 +73,7 @@ RESPONSE_RE = _re.compile( # ───────────────────────────────────────────────────────────────────────────── def load_regexes(path: str) -> list[str]: - """Parse regexes.txt — skip blank lines and comments.""" + """Parse regexes.txt - skip blank lines and comments.""" patterns = [] try: with open(path) as f: @@ -158,7 +158,7 @@ def reader_thread( state.update_from_response(line, sent) except serial.SerialException: with state.lock: - state.status_msg = "Serial error — disconnected" + state.status_msg = "Serial error - disconnected" state.connected = False break except Exception: @@ -203,7 +203,7 @@ def build_match_table(state: MatchState, patterns: list[str]) -> Table: if matched: match_cell = Text("● MATCH", style="bold green") else: - match_cell = Text("○ —", style="dim red") + match_cell = Text("○ - ", style="dim red") row_data.extend( [ @@ -225,7 +225,7 @@ def build_stats_panel(state: MatchState) -> Panel: with state.lock: bc = state.byte_count last_s = state.last_string or "(none)" - raw = state.last_response_raw or "—" + raw = state.last_response_raw or "- " status = state.status_msg conn = state.connected diff --git a/tui/pii_demo.py b/tui/pii_demo.py @@ -0,0 +1,81 @@ +import serial +import time +import sys + +# Set port depending on OS/Setup (Eg. /dev/ttyUSB1) +PORT = "COM4" +BAUD = 921600 + +try: + ser = serial.Serial(PORT, 115200, timeout=1, rtscts=False) +except Exception as e: + print(f"ERROR: Could not open {PORT}: {e}") + if "Permission denied" in str(e): + print(f"HINT: Try running with sudo: 'sudo ./venv/bin/python pii_demo.py'") + print("\n--- FALLING BACK TO MOCK MODE (Simulation) ---") + ser = None + + +def mock_redact(text): + import re + + # Simplified simulation of the FPGA patterns + patterns = [ + r"[a-zA-Z0-9.]+@[a-zA-Z0-9.]+\.[a-zA-Z]+", # Email + r"\d{10}", # Phone + r"\d{3}-\d{2}-\d{4}", # SSN + r"\d{16}", # CC + ] + redacted = text + for p in patterns: + for match in re.finditer(p, redacted): + start, end = match.span() + redacted = redacted[:start] + "X" * (end - start) + redacted[end:] + return redacted + + +def stream_text(text): + print(f"Original Stream: {text}\n") + + if ser: + print("Redacted Stream: ", end="", flush=True) + ser.reset_input_buffer() + + has_started = False + for char in text: + ser.write(char.encode()) + scrubbed = ser.read(1).decode("utf-8", errors="replace") + + # Skip leading spaces from the delay buffer initialization + if not has_started and scrubbed != " ": + has_started = True + + if has_started: + print(scrubbed, end="", flush=True) + + time.sleep(0.002) # Faster streaming for large demo files + else: + print("(MOCK) Redacted Stream: ", end="", flush=True) + simulated = mock_redact(text) + for char in simulated: + print(char, end="", flush=True) + time.sleep(0.01) + + print("\n\nDone.") + + +if __name__ == "__main__": + import os + + file_path = ( + "demo_input.txt" + if os.path.exists("demo_input.txt") + else "../pii/demo_input.txt" + ) + if not os.path.exists(file_path): + file_path = "pii/demo_input.txt" + with open(file_path, "r") as f: + demo_text = f.read() + + # Add 128 spaces to flush the FPGA's 128-char delay buffer + stream_text(demo_text + " " * 128) diff --git a/tui/requirements.txt b/tui/requirements.txt @@ -0,0 +1,3 @@ +pyserial +rich +textual