xiiregexbuilder

 1# VIVADO SYNTHESIS & BITSTREAM SCRIPT
 2# This script automates the flow for the PII Guard Demo
 3
 4# 1. Define target part
 5set part xc7a100tcsg324-1
 6set outputDir ./build
 7file mkdir $outputDir
 8
 9# 2. Create the project in memory
10create_project -in_memory -part $part
11
12# 3. Read Verilog Files
13read_verilog [glob output/*.v]
14
15# 4. Read Constraints
16read_xdc output/constraints.xdc
17
18# 5. Run Synthesis
19synth_design -top top_fpga -part $part
20
21# 6. Run Implementation Flow
22opt_design
23place_design
24route_design
25
26# 7. Generate Reports
27report_utilization -file $outputDir/post_route_util.txt
28report_timing_summary -file $outputDir/post_route_timing.txt
29
30# 8. Generate Bitstream
31write_bitstream -force $outputDir/top_fpga.bit
32
33# 9. Cleanup and close
34close_project