xiiregexbuilder

commit 10295686a022feddee6768c9b2a04d20e4e8d9c0
parent c72154b995239edb5f06e280d9db90b8f9ed6087
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date:   Wed, 22 Apr 2026 12:29:59 +0530

Week 6: UART modules, example testbench, and repository configuration (Part 1: Initial definitions)

Diffstat:
M
.gitignore
 | 
10
++++++++--
M
Makefile
 | 
12
++++++++++--

2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/.gitignore b/.gitignore
@@ -39,18 +39,24 @@
 
 # Debug information
 *.dwo
-output/
 
 # Final Executable
 build/
+output/
 
 # Vivado Files
 *.bit
 *.jou
 *.log
+*.pb
+*.wdb
+*.str
+.Xil/
+xsim.dir/
 clockInfo.txt
 dfx_runtime.txt
-.Xil/
+usage_statistics_webtalk.*
 
 # Python TUI
 .venv
+__pycache__/
diff --git a/Makefile b/Makefile
@@ -122,13 +122,21 @@ proc_synth: proc_asm | $(PROC_BUILD_DIR)
 proc_program:
 	$(MAKE) program BITSTREAM=$(PROC_BUILD_DIR)/top_fpga.bit
 
+# PII Guard Targets
+pii_build: all | $(OUTPUT_DIR)
+	$(TARGET) --pii pii/pii_regexes.txt $(INPUT_DIR)/test_strings.txt $(OUTPUT_DIR)
+
+pii_synth: pii_build
+	@echo "Launching Vivado Synthesis Flow for PII Guard..."
+	$(VIVADO_PATH) -mode batch -source $(call FIX_PATH,scripts/synth_pii.tcl)
+
 clean:
 	-$(RM) $(call FIX_PATH,src/*.o)
 	-$(RMDIR) $(call FIX_PATH,$(BUILD_DIR))
 	-$(RMDIR) $(call FIX_PATH,$(OUTPUT_DIR))
 	-$(RMDIR) $(call FIX_PATH,processor/build)
 	-$(RM) *.bit *.log *.jou *.pb *.wdb *.str usage_statistics_webtalk.*
-	-$(RM) clockInfo.txt dfx_runtime.txt
+	-$(RM) clockInfo.txt dfx_runtime.txt *.hex *.exe
 	-$(RMDIR) xsim.dir .Xil
 
-.PHONY: all run test golden synth program proc_asm proc_sim proc_update_regex proc_synth proc_program clean
+.PHONY: all run test golden synth program proc_asm proc_sim proc_update_regex proc_synth proc_program pii_build pii_synth clean