xiiregexbuilder

commit 48a66bfc500eef570ceebbc96de93a37d04adcf0
parent c636ad41973ea81ab3b19a920d273e9607e54421
Author: Achuthan TM <achuthantm05@gmail.com>
Date:   Wed,  8 Apr 2026 22:00:00 +0530

Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 3: Finalizing)

Diffstat:
A
output-eg/nfa_5.v
 | 
47
+++++++++++++++++++++++++++++++++++++++++++++++
A
scripts/synth.tcl
 | 
40
++++++++++++++++++++++++++++++++++++++++

2 files changed, 87 insertions(+), 0 deletions(-)
diff --git a/output-eg/nfa_5.v b/output-eg/nfa_5.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 5
+module nfa_5 (
+    input  wire       clk,
+    input  wire       en,
+    input  wire       rst,
+    input  wire       start,
+    input  wire       end_of_str,
+    input  wire [7:0] char_in,
+    output reg        match
+);
+
+    // One-hot state register
+    reg [5:0] state_reg;
+    wire [5:0] next_state;
+
+    assign next_state[0] = 1'b0;
+    assign next_state[1] = (state_reg[0] && (char_in == 8'd97)) | (state_reg[1] && (char_in == 8'd97)) | (state_reg[2] && (char_in == 8'd97));
+    assign next_state[2] = (state_reg[0] && (char_in == 8'd98)) | (state_reg[1] && (char_in == 8'd98)) | (state_reg[2] && (char_in == 8'd98));
+    assign next_state[3] = (state_reg[0] && (char_in == 8'd99)) | (state_reg[1] && (char_in == 8'd99)) | (state_reg[2] && (char_in == 8'd99));
+    assign next_state[4] = (state_reg[3] && (char_in == 8'd100)) | (state_reg[4] && (char_in == 8'd100)) | (state_reg[5] && (char_in == 8'd100));
+    assign next_state[5] = (state_reg[3] && (char_in == 8'd101)) | (state_reg[4] && (char_in == 8'd101)) | (state_reg[5] && (char_in == 8'd101));
+
+    always @(posedge clk) begin
+        if (rst || start) begin
+            // Reset to start state (one-hot)
+            state_reg <= 1 << 0;
+        end else if (en) begin
+            state_reg <= next_state;
+        end
+    end
+
+    // Match logic: asserted on cycle following end_of_str
+    always @(posedge clk) begin
+        if (rst || start) begin
+            match <= 1'b0;
+        end else if (en) begin
+            if (end_of_str) begin
+                match <= (|{state_reg[4], state_reg[5]});
+            end else begin
+                match <= 1'b0;
+            end
+        end
+    end
+
+endmodule
diff --git a/scripts/synth.tcl b/scripts/synth.tcl
@@ -0,0 +1,40 @@
+# VIVADO SYNTHESIS & BITSTREAM SCRIPT
+# This script automates the flow for the generated Regex Matcher hardware
+
+# 1. Define target part (Nexys A7 100T)
+set part xc7a100tcsg324-1
+set outputDir ./build
+file mkdir $outputDir
+
+# 2. Create the project in memory
+create_project -in_memory -part $part
+
+# 3. Read all Verilog files
+# All Verilog files listed here are generated by `make run`
+read_verilog [glob output/nfa_*.v]
+read_verilog output/top.v
+read_verilog output/uart_rx.v
+read_verilog output/uart_tx.v
+read_verilog output/uart_rx_fifo.v
+read_verilog output/top_fpga.v
+
+# 4. Read Constraints
+read_xdc output/constraints.xdc
+
+# 5. Run Synthesis
+synth_design -top top_fpga -part $part
+
+# 6. Run Implementation Flow
+opt_design
+place_design
+route_design
+
+# 7. Generate Reports
+report_utilization    -file $outputDir/post_route_util.txt
+report_timing_summary -file $outputDir/post_route_timing.txt
+
+# 8. Generate Bitstream
+write_bitstream -force top_fpga.bit
+
+# 9. Cleanup and close
+close_project