xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3// NFA for regex index 5
 4module nfa_5 (
 5    input  wire       clk,
 6    input  wire       en,
 7    input  wire       rst,
 8    input  wire       start,
 9    input  wire       end_of_str,
10    input  wire [7:0] char_in,
11    output reg        match,
12    output wire       active
13);
14
15    // One-hot state register
16    reg [11:0] state_reg;
17    wire [11:0] next_state;
18
19    assign next_state[0] = 1'b0;
20    assign next_state[1] = (state_reg[0] && (char_in == 8'd97));
21    assign next_state[2] = (state_reg[1] && (char_in == 8'd112));
22    assign next_state[3] = (state_reg[2] && (char_in == 8'd112));
23    assign next_state[4] = (state_reg[3] && (char_in == 8'd108));
24    assign next_state[5] = (state_reg[4] && (char_in == 8'd101));
25    assign next_state[6] = (state_reg[0] && (char_in == 8'd111));
26    assign next_state[7] = (state_reg[6] && (char_in == 8'd114));
27    assign next_state[8] = (state_reg[7] && (char_in == 8'd97));
28    assign next_state[9] = (state_reg[8] && (char_in == 8'd110));
29    assign next_state[10] = (state_reg[9] && (char_in == 8'd103));
30    assign next_state[11] = (state_reg[10] && (char_in == 8'd101));
31
32    always @(posedge clk) begin
33        if (rst || start) begin
34            // Reset to start state (one-hot)
35            state_reg <= 1 << 0;
36        end else if (en) begin
37            state_reg <= next_state;
38        end
39    end
40
41    // Match logic: asserted on cycle following end_of_str
42    always @(posedge clk) begin
43        if (rst || start) begin
44            match <= 1'b0;
45        end else if (en) begin
46            if (end_of_str) begin
47                match <= (|{state_reg[5], state_reg[11]});
48            end else begin
49                match <= 1'b0;
50            end
51        end
52    end
53
54    // Active logic: high if any state other than state 0 is active
55    assign active = |state_reg[11:1];
56
57endmodule