xiiregexbuilder

 1# VIVADO SYNTHESIS & BITSTREAM SCRIPT
 2# This script automates the flow for the generated Regex Matcher hardware
 3
 4# 1. Setup
 5set part xc7a100tcsg324-1
 6set outputDir ./build
 7file mkdir $outputDir
 8
 9# 2. Create the project in memory
10create_project -in_memory -part $part
11
12# 3. Read Verilog files
13# All Verilog files listed here are generated by `make run`
14read_verilog [glob output/nfa_*.v]
15read_verilog output/top.v
16read_verilog output/uart_rx.v
17read_verilog output/uart_tx.v
18read_verilog output/uart_rx_fifo.v
19read_verilog output/top_fpga.v
20
21# 4. Read Constraints
22read_xdc output/constraints.xdc
23
24# 5. Run Synthesis
25synth_design -top top_fpga -part $part
26
27# 6. Run Implementation Flow
28opt_design
29place_design
30route_design
31
32# 7. Generate Reports
33report_utilization    -file $outputDir/post_route_util.txt
34report_timing_summary -file $outputDir/post_route_timing.txt
35
36# 8. Generate Bitstream
37write_bitstream -force $outputDir/top_fpga.bit
38
39# 9. Cleanup and close
40close_project