commit 3ad17970a37887e3110e5203d3ad0a741c345d88
parent 471ae799ee654084667d3635fd959ca9f4e0b452
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date: Fri, 24 Apr 2026 14:59:59 +0530
Week 6: UART modules, example testbench, and repository configuration (Part 3: Finalizing)
Diffstat:
2 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/output-pii/uart_rx.v b/output-pii/uart_rx.v
@@ -0,0 +1,54 @@
+`timescale 1ns / 1ps
+
+
+module uart_rx #(
+ parameter CLKS_PER_BIT = 868 // 100 MHz / 115200 Baud
+)(
+ input wire clk,
+ input wire rx,
+ output reg [7:0] rx_data,
+ output reg rx_ready
+);
+ localparam IDLE = 2'b00, START_BIT = 2'b01, DATA_BITS = 2'b10, STOP_BIT = 2'b11;
+ reg [1:0] state = IDLE;
+ reg [9:0] clk_count = 0;
+ reg [2:0] bit_idx = 0;
+
+ always @(posedge clk) begin
+ case (state)
+ IDLE: begin
+ rx_ready <= 1'b0;
+ clk_count <= 0;
+ bit_idx <= 0;
+ if (rx == 1'b0) state <= START_BIT;
+ end
+ START_BIT: begin
+ if (clk_count == (CLKS_PER_BIT-1)/2) begin
+ if (rx == 1'b0) begin
+ clk_count <= 0;
+ state <= DATA_BITS;
+ end else state <= IDLE;
+ end else clk_count <= clk_count + 1;
+ end
+ DATA_BITS: begin
+ if (clk_count < CLKS_PER_BIT-1) begin
+ clk_count <= clk_count + 1;
+ end else begin
+ clk_count <= 0;
+ rx_data[bit_idx] <= rx;
+ if (bit_idx < 7) bit_idx <= bit_idx + 1;
+ else state <= STOP_BIT;
+ end
+ end
+ STOP_BIT: begin
+ if (clk_count < CLKS_PER_BIT-1) begin
+ clk_count <= clk_count + 1;
+ end else begin
+ // FIX: Check for framing error
+ if (rx == 1'b1) rx_ready <= 1'b1;
+ state <= IDLE;
+ end
+ end
+ endcase
+ end
+endmodule
diff --git a/output-pii/uart_tx.v b/output-pii/uart_tx.v
@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+
+
+module uart_tx #(
+ parameter CLKS_PER_BIT = 868 // 100 MHz / 115200 Baud
+)(
+ input wire clk,
+ input wire tx_start,
+ input wire [7:0] tx_data,
+ output reg tx,
+ output reg tx_busy
+);
+ localparam IDLE = 2'b00, START_BIT = 2'b01, DATA_BITS = 2'b10, STOP_BIT = 2'b11;
+ reg [1:0] state = IDLE;
+ reg [9:0] clk_count = 0;
+ reg [2:0] bit_idx = 0;
+ reg [7:0] tx_data_latch = 0;
+
+ initial begin
+ tx = 1'b1;
+ tx_busy = 1'b0;
+ end
+
+ always @(posedge clk) begin
+ case (state)
+ IDLE: begin
+ tx <= 1'b1;
+ tx_busy <= 1'b0;
+ if (tx_start) begin
+ tx_data_latch <= tx_data;
+ tx_busy <= 1'b1;
+ state <= START_BIT;
+ clk_count <= 0;
+ end
+ end
+ START_BIT: begin
+ tx <= 1'b0;
+ if (clk_count < CLKS_PER_BIT-1) begin
+ clk_count <= clk_count + 1;
+ end else begin
+ clk_count <= 0;
+ bit_idx <= 0;
+ state <= DATA_BITS;
+ end
+ end
+ DATA_BITS: begin
+ tx <= tx_data_latch[bit_idx];
+ if (clk_count < CLKS_PER_BIT-1) begin
+ clk_count <= clk_count + 1;
+ end else begin
+ clk_count <= 0;
+ if (bit_idx < 7) bit_idx <= bit_idx + 1;
+ else state <= STOP_BIT;
+ end
+ end
+ STOP_BIT: begin
+ tx <= 1'b1;
+ if (clk_count < CLKS_PER_BIT-1) begin
+ clk_count <= clk_count + 1;
+ end else begin
+ state <= IDLE;
+ end
+ end
+ endcase
+ end
+endmodule