xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3
 4module uart_tx #(
 5    parameter CLKS_PER_BIT = 868 // 100 MHz / 115200 Baud
 6)(
 7    input  wire       clk,
 8    input  wire       tx_start,
 9    input  wire [7:0] tx_data,
10    output reg        tx,
11    output reg        tx_busy
12);
13    localparam IDLE = 2'b00, START_BIT = 2'b01, DATA_BITS = 2'b10, STOP_BIT = 2'b11;
14    reg [1:0] state = IDLE;
15    reg [9:0] clk_count = 0;
16    reg [2:0] bit_idx = 0;
17    reg [7:0] tx_data_latch = 0;
18
19    initial begin
20        tx = 1'b1;
21        tx_busy = 1'b0;
22    end
23
24    always @(posedge clk) begin
25        case (state)
26            IDLE: begin
27                tx <= 1'b1;
28                tx_busy <= 1'b0;
29                if (tx_start) begin
30                    tx_data_latch <= tx_data;
31                    tx_busy <= 1'b1;
32                    state <= START_BIT;
33                    clk_count <= 0;
34                end
35            end
36            START_BIT: begin
37                tx <= 1'b0;
38                if (clk_count < CLKS_PER_BIT-1) begin
39                    clk_count <= clk_count + 1;
40                end else begin
41                    clk_count <= 0;
42                    bit_idx <= 0;
43                    state <= DATA_BITS;
44                end
45            end
46            DATA_BITS: begin
47                tx <= tx_data_latch[bit_idx];
48                if (clk_count < CLKS_PER_BIT-1) begin
49                    clk_count <= clk_count + 1;
50                end else begin
51                    clk_count <= 0;
52                    if (bit_idx < 7) bit_idx <= bit_idx + 1;
53                    else state <= STOP_BIT;
54                end
55            end
56            STOP_BIT: begin
57                tx <= 1'b1;
58                if (clk_count < CLKS_PER_BIT-1) begin
59                    clk_count <= clk_count + 1;
60                end else begin
61                    state <= IDLE;
62                end
63            end
64        endcase
65    end
66endmodule