xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3
 4module uart_rx #(
 5    parameter CLKS_PER_BIT = 868 // 100 MHz / 115200 Baud
 6)(
 7    input  wire       clk,
 8    input  wire       rx,
 9    output reg  [7:0] rx_data,
10    output reg        rx_ready
11);
12    localparam IDLE = 2'b00, START_BIT = 2'b01, DATA_BITS = 2'b10, STOP_BIT = 2'b11;
13    reg [1:0] state = IDLE;
14    reg [9:0] clk_count = 0;
15    reg [2:0] bit_idx = 0;
16
17    always @(posedge clk) begin
18        case (state)
19            IDLE: begin
20                rx_ready <= 1'b0;
21                clk_count <= 0;
22                bit_idx <= 0;
23                if (rx == 1'b0) state <= START_BIT;
24            end
25            START_BIT: begin
26                if (clk_count == (CLKS_PER_BIT-1)/2) begin
27                    if (rx == 1'b0) begin
28                        clk_count <= 0;
29                        state <= DATA_BITS;
30                    end else state <= IDLE;
31                end else clk_count <= clk_count + 1;
32            end
33            DATA_BITS: begin
34                if (clk_count < CLKS_PER_BIT-1) begin
35                    clk_count <= clk_count + 1;
36                end else begin
37                    clk_count <= 0;
38                    rx_data[bit_idx] <= rx;
39                    if (bit_idx < 7) bit_idx <= bit_idx + 1;
40                    else state <= STOP_BIT;
41                end
42            end
43            STOP_BIT: begin
44                if (clk_count < CLKS_PER_BIT-1) begin
45                    clk_count <= clk_count + 1;
46                end else begin
47                    // FIX: Check for framing error
48                    if (rx == 1'b1) rx_ready <= 1'b1; 
49                    state <= IDLE;
50                end
51            end
52        endcase
53    end
54endmodule