commit e4e352a8a144e54b5a12b961d025aa270a6daba8
parent 18530b5463446ce65ca3c26acd1aa15243b99892
Author: RahulSannapureddy <rahul.sannapureddy@gmail.com>
Date: Sun, 19 Apr 2026 18:30:00 +0530
Week 5: Peripheral integration, testbenches and simulation inputs (Part 3: Finalizing)
Diffstat:
2 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/scripts/synth.tcl b/scripts/synth.tcl
@@ -1,7 +1,7 @@
# VIVADO SYNTHESIS & BITSTREAM SCRIPT
# This script automates the flow for the generated Regex Matcher hardware
-# 1. Define target part (Nexys A7 100T)
+# 1. Setup
set part xc7a100tcsg324-1
set outputDir ./build
file mkdir $outputDir
@@ -9,7 +9,7 @@ file mkdir $outputDir
# 2. Create the project in memory
create_project -in_memory -part $part
-# 3. Read all Verilog files
+# 3. Read Verilog files
# All Verilog files listed here are generated by `make run`
read_verilog [glob output/nfa_*.v]
read_verilog output/top.v
@@ -34,7 +34,7 @@ report_utilization -file $outputDir/post_route_util.txt
report_timing_summary -file $outputDir/post_route_timing.txt
# 8. Generate Bitstream
-write_bitstream -force top_fpga.bit
+write_bitstream -force $outputDir/top_fpga.bit
# 9. Cleanup and close
close_project
diff --git a/scripts/synth_proc.tcl b/scripts/synth_proc.tcl
@@ -0,0 +1,35 @@
+# VIVADO SYNTHESIS & BITSTREAM SCRIPT
+# This script automates the flow for the Regex Processor hardware
+
+# 1. Setup
+set part xc7a100tcsg324-1
+set outputDir ./processor/build
+file mkdir $outputDir
+
+# 2. Read Verilog files
+read_verilog processor/regex_cpu.v
+read_verilog processor/uart.v
+read_verilog processor/top_level.v
+
+# 3. Read Constraints
+read_xdc processor/constraints.xdc
+
+# 4. Add memory files
+set_property DESIGN_MODE RTL [current_fileset]
+add_files -norecurse processor/build/imem.hex
+set_property file_type {Memory Initialization Files} [get_files processor/build/imem.hex]
+
+# 5. Run Synthesis
+synth_design -top top_level -part $part
+
+# 6. Run Implementation Flow
+opt_design
+place_design
+route_design
+
+# 7. Generate Reports
+report_utilization -file $outputDir/utilization.txt
+report_timing_summary -file $outputDir/timing.txt
+
+# 8. Generate Bitstream
+write_bitstream -force $outputDir/top_fpga.bit