xiiregexbuilder

 1# VIVADO SYNTHESIS & BITSTREAM SCRIPT
 2# This script automates the flow for the Regex Processor hardware
 3
 4# 1. Setup
 5set part xc7a100tcsg324-1
 6set outputDir ./processor/build
 7file mkdir $outputDir
 8
 9# 2. Read Verilog files
10read_verilog processor/regex_cpu.v
11read_verilog processor/uart.v
12read_verilog processor/top_level.v
13
14# 3. Read Constraints
15read_xdc processor/constraints.xdc
16
17# 4. Add memory files
18set_property DESIGN_MODE RTL [current_fileset]
19add_files -norecurse processor/build/imem.hex
20set_property file_type {Memory Initialization Files} [get_files processor/build/imem.hex]
21
22# 5. Run Synthesis
23synth_design -top top_level -part $part
24
25# 6. Run Implementation Flow
26opt_design
27place_design
28route_design
29
30# 7. Generate Reports
31report_utilization -file $outputDir/utilization.txt
32report_timing_summary -file $outputDir/timing.txt
33
34# 8. Generate Bitstream
35write_bitstream -force $outputDir/top_fpga.bit