xiiregexbuilder

commit be037ac565931db31a2ec30e4e8376a364fe7c24
parent 586ee1dc397750bfdc9014fa5902015ee4cf2e4a
Author: Achuthan TM <achuthantm05@gmail.com>
Date:   Fri,  3 Apr 2026 05:49:33 +0530

Week 3: Generate first batch of NFA Verilog modules (Part 2: Core logic)

Diffstat:
A
output-eg/nfa_1.v
 | 
45
+++++++++++++++++++++++++++++++++++++++++++++

1 file changed, 45 insertions(+), 0 deletions(-)
diff --git a/output-eg/nfa_1.v b/output-eg/nfa_1.v
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 1
+module nfa_1 (
+    input  wire       clk,
+    input  wire       en,
+    input  wire       rst,
+    input  wire       start,
+    input  wire       end_of_str,
+    input  wire [7:0] char_in,
+    output reg        match
+);
+
+    // One-hot state register
+    reg [3:0] state_reg;
+    wire [3:0] next_state;
+
+    assign next_state[0] = 1'b0;
+    assign next_state[1] = (state_reg[0] && (char_in == 8'd97));
+    assign next_state[2] = (state_reg[1] && (char_in == 8'd98)) | (state_reg[2] && (char_in == 8'd98));
+    assign next_state[3] = (state_reg[1] && (char_in == 8'd99)) | (state_reg[2] && (char_in == 8'd99));
+
+    always @(posedge clk) begin
+        if (rst || start) begin
+            // Reset to start state (one-hot)
+            state_reg <= 1 << 0;
+        end else if (en) begin
+            state_reg <= next_state;
+        end
+    end
+
+    // Match logic: asserted on cycle following end_of_str
+    always @(posedge clk) begin
+        if (rst || start) begin
+            match <= 1'b0;
+        end else if (en) begin
+            if (end_of_str) begin
+                match <= state_reg[3];
+            end else begin
+                match <= 1'b0;
+            end
+        end
+    end
+
+endmodule