xiiregexbuilder

commit 586ee1dc397750bfdc9014fa5902015ee4cf2e4a
parent abc269ec4be88de2485c8ef07ca7e78a50fb3448
Author: yash modi <yash3108m@gmail.com>
Date:   Thu,  2 Apr 2026 23:33:54 +0530

Week 3: Implement UART RX hardware FIFO (Part 3: Finalizing)

Diffstat:
M
output-eg/uart_rx_fifo.v
 | 
11
+++++++++++

1 file changed, 11 insertions(+), 0 deletions(-)
diff --git a/output-eg/uart_rx_fifo.v b/output-eg/uart_rx_fifo.v
@@ -34,3 +34,14 @@ module uart_rx_fifo #(
                 mem[wr_ptr] <= wr_data;
                 wr_ptr      <= wr_ptr + 1;
                 rd_ptr      <= rd_ptr + 1;
+            end else if (wr_en && !full) begin
+                mem[wr_ptr] <= wr_data;
+                wr_ptr      <= wr_ptr + 1;
+                count       <= count + 1;
+            end else if (rd_en && !empty) begin
+                rd_ptr <= rd_ptr + 1;
+                count  <= count - 1;
+            end
+        end
+    end
+endmodule