xiiregexbuilder

commit a40c44015b4f5a32571357cff412dde8766ac468
parent b58127612186e2684a3aa3cb4ebc4574c9926a8c
Author: yash modi <yash3108m@gmail.com>
Date:   Thu,  2 Apr 2026 11:02:36 +0530

Week 3: Implement UART RX hardware FIFO (Part 2: Core logic)

Diffstat:
M
output-eg/uart_rx_fifo.v
 | 
21
+++++++++++++++++++++

1 file changed, 21 insertions(+), 0 deletions(-)
diff --git a/output-eg/uart_rx_fifo.v b/output-eg/uart_rx_fifo.v
@@ -13,3 +13,24 @@ module uart_rx_fifo #(
     input  wire       rd_en,
     output wire       empty
 );
+    localparam DEPTH = 1 << DEPTH_LOG2;
+
+    reg [7:0] mem [0:DEPTH-1];
+    reg [DEPTH_LOG2-1:0] wr_ptr = {DEPTH_LOG2{1'b0}};
+    reg [DEPTH_LOG2-1:0] rd_ptr = {DEPTH_LOG2{1'b0}};
+    reg [DEPTH_LOG2  :0] count  = {(DEPTH_LOG2+1){1'b0}};
+
+    assign full    = (count == DEPTH[DEPTH_LOG2:0]);
+    assign empty   = (count == {(DEPTH_LOG2+1){1'b0}});
+    assign rd_data = mem[rd_ptr];
+
+    always @(posedge clk) begin
+        if (rst) begin
+            wr_ptr <= {DEPTH_LOG2{1'b0}};
+            rd_ptr <= {DEPTH_LOG2{1'b0}};
+            count  <= {(DEPTH_LOG2+1){1'b0}};
+        end else begin
+            if (wr_en && !full && rd_en && !empty) begin
+                mem[wr_ptr] <= wr_data;
+                wr_ptr      <= wr_ptr + 1;
+                rd_ptr      <= rd_ptr + 1;