xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3
 4module uart_rx_fifo #(
 5    parameter DEPTH_LOG2 = 4        // depth = 2^DEPTH_LOG2 = 16
 6)(
 7    input  wire       clk,
 8    input  wire       rst,
 9    input  wire [7:0] wr_data,
10    input  wire       wr_en,
11    output wire       full,
12    output wire [7:0] rd_data,
13    input  wire       rd_en,
14    output wire       empty
15);
16    localparam DEPTH = 1 << DEPTH_LOG2;
17
18    reg [7:0] mem [0:DEPTH-1];
19    reg [DEPTH_LOG2-1:0] wr_ptr = {DEPTH_LOG2{1'b0}};
20    reg [DEPTH_LOG2-1:0] rd_ptr = {DEPTH_LOG2{1'b0}};
21    reg [DEPTH_LOG2  :0] count  = {(DEPTH_LOG2+1){1'b0}};
22
23    assign full    = (count == DEPTH[DEPTH_LOG2:0]);
24    assign empty   = (count == {(DEPTH_LOG2+1){1'b0}});
25    assign rd_data = mem[rd_ptr];
26
27    always @(posedge clk) begin
28        if (rst) begin
29            wr_ptr <= {DEPTH_LOG2{1'b0}};
30            rd_ptr <= {DEPTH_LOG2{1'b0}};
31            count  <= {(DEPTH_LOG2+1){1'b0}};
32        end else begin
33            if (wr_en && !full && rd_en && !empty) begin
34                mem[wr_ptr] <= wr_data;
35                wr_ptr      <= wr_ptr + 1;
36                rd_ptr      <= rd_ptr + 1;
37            end else if (wr_en && !full) begin
38                mem[wr_ptr] <= wr_data;
39                wr_ptr      <= wr_ptr + 1;
40                count       <= count + 1;
41            end else if (rd_en && !empty) begin
42                rd_ptr <= rd_ptr + 1;
43                count  <= count - 1;
44            end
45        end
46    end
47endmodule