xiiregexbuilder

commit 1afac9076b61391997f852de92a74d1fb2e9e75b
parent be037ac565931db31a2ec30e4e8376a364fe7c24
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date:   Fri,  3 Apr 2026 12:05:13 +0530

Week 3: Initial Verilog top wrapper and UART TX (Part 3: Finalizing)

Diffstat:
M
output-eg/top.v
 | 
9
+++++++++
M
output-eg/uart_tx.v
 | 
19
+++++++++++++++++++

2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/output-eg/top.v b/output-eg/top.v
@@ -26,3 +26,12 @@ module top (
         .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[3])
     );
 
+    nfa_4 inst_4 (
+        .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[4])
+    );
+
+    nfa_5 inst_5 (
+        .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[5])
+    );
+
+endmodule
diff --git a/output-eg/uart_tx.v b/output-eg/uart_tx.v
@@ -61,3 +61,22 @@ module uart_tx #(
                         if (bit_idx < 7)
                             bit_idx <= bit_idx + 1;
                         else begin
+                            bit_idx <= 3'd0;
+                            state   <= S_STOP_BIT;
+                        end
+                    end
+                end
+                S_STOP_BIT: begin
+                    tx <= 1'b1;
+                    if (clk_cnt < CLKS_PER_BIT - 1)
+                        clk_cnt <= clk_cnt + 1;
+                    else begin
+                        clk_cnt <= 10'd0;
+                        state   <= S_IDLE;
+                    end
+                end
+                default: state <= S_IDLE;
+            endcase
+        end
+    end
+endmodule