xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3
 4module uart_tx #(
 5    parameter CLKS_PER_BIT = 868   // 100 MHz / 115200 baud
 6)(
 7    input  wire       clk,
 8    input  wire       rst,
 9    input  wire [7:0] tx_data,
10    input  wire       tx_start,
11    output reg        tx_busy,
12    output reg        tx
13);
14    localparam S_IDLE      = 3'd0;
15    localparam S_START_BIT = 3'd1;
16    localparam S_DATA_BITS = 3'd2;
17    localparam S_STOP_BIT  = 3'd3;
18
19    reg [2:0]  state    = S_IDLE;
20    reg [9:0]  clk_cnt  = 10'd0;
21    reg [2:0]  bit_idx  = 3'd0;
22    reg [7:0]  tx_shift = 8'd0;
23
24    always @(posedge clk) begin
25        if (rst) begin
26            state    <= S_IDLE;
27            tx       <= 1'b1;
28            tx_busy  <= 1'b0;
29            clk_cnt  <= 10'd0;
30            bit_idx  <= 3'd0;
31            tx_shift <= 8'd0;
32        end else begin
33            case (state)
34                S_IDLE: begin
35                    tx      <= 1'b1;
36                    tx_busy <= 1'b0;
37                    clk_cnt <= 10'd0;
38                    bit_idx <= 3'd0;
39                    if (tx_start) begin
40                        tx_shift <= tx_data;
41                        tx_busy  <= 1'b1;
42                        state    <= S_START_BIT;
43                    end
44                end
45                S_START_BIT: begin
46                    tx <= 1'b0;
47                    if (clk_cnt < CLKS_PER_BIT - 1)
48                        clk_cnt <= clk_cnt + 1;
49                    else begin
50                        clk_cnt <= 10'd0;
51                        state   <= S_DATA_BITS;
52                    end
53                end
54                S_DATA_BITS: begin
55                    tx <= tx_shift[0];
56                    if (clk_cnt < CLKS_PER_BIT - 1)
57                        clk_cnt <= clk_cnt + 1;
58                    else begin
59                        clk_cnt  <= 10'd0;
60                        tx_shift <= tx_shift >> 1;
61                        if (bit_idx < 7)
62                            bit_idx <= bit_idx + 1;
63                        else begin
64                            bit_idx <= 3'd0;
65                            state   <= S_STOP_BIT;
66                        end
67                    end
68                end
69                S_STOP_BIT: begin
70                    tx <= 1'b1;
71                    if (clk_cnt < CLKS_PER_BIT - 1)
72                        clk_cnt <= clk_cnt + 1;
73                    else begin
74                        clk_cnt <= 10'd0;
75                        state   <= S_IDLE;
76                    end
77                end
78                default: state <= S_IDLE;
79            endcase
80        end
81    end
82endmodule