xiiregexbuilder

commit f4f8ccdf923532ea7e9a579c6ad460a33c6fc08c
parent a2fa577fb0c3bb5a176b4668f71d69a28eb2cc2b
Author: yash modi <yash3108m@gmail.com>
Date:   Tue, 24 Mar 2026 16:51:25 +0530

Week 1: Define Verilog Emitter headers (Part 3: Finalizing)

Diffstat:
M
src/emitter.h
 | 
12
++++++++++++

1 file changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/emitter.h b/src/emitter.h
@@ -38,3 +38,15 @@ private:
     static void emitUARTRX(const std::filesystem::path &outputDir);
 
     // UART TX transmitter
+    static void emitUARTTX(const std::filesystem::path &outputDir);
+
+    // Circular FIFO buffer between uart_rx and the NFA engine
+    static void emitFIFO(const std::filesystem::path &outputDir);
+
+    // Top FPGA module
+    static void emitTopFPGA(const std::vector<std::unique_ptr<NFA>> &nfas, const std::filesystem::path &outputDir);
+
+    static void emitConstraints(const std::vector<std::unique_ptr<NFA>> &nfas, const std::filesystem::path &outputDir);
+};
+
+#endif // EMITTER_H