commit db8fb4edf3854d38715e2052d42f57c6ccaacff9 parent 6bde5feec6bac8e253cb94ca9521b486037a80c3 Author: yash modi <yash3108m@gmail.com> Date: Mon, 13 Apr 2026 23:49:17 +0530 Week 5: Core processor logic and parallel engine implementation (Part 2: Core logic) Diffstat:
| M | docs/usecases.md | | | 2 | ++ |
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/docs/usecases.md b/docs/usecases.md @@ -18,6 +18,8 @@ Modern financial markets generate enormous volumes of structured text — orders **Trade Surveillance and Compliance.** Patterns like spoofing, layering, and wash trading are detectable as sequences in live order flow. Hardware matching enables real-time compliance checks on the live feed rather than retrospective analysis on stored logs. +**Dynamic Strategy Adjustment.** Financial conditions shift in milliseconds. The **Soft-Processor engine** allows traders to update their regex filtering rules on-the-fly without needing to take the system offline for a slow hardware re-synthesis. This combination of hardware speed and software flexibility is a unique advantage of our dual-architecture approach. + --- ## Why FPGA and Not Just Faster Software?