commit c72154b995239edb5f06e280d9db90b8f9ed6087
parent ce33559706c8ba674c609821d7a40417efd668fe
Author: yash modi <yash3108m@gmail.com>
Date: Wed, 22 Apr 2026 05:17:08 +0530
Week 6: Verilog NFA generation for example regexes and project specifications (Part 2: Core logic)
Diffstat:
6 files changed, 216 insertions(+), 9 deletions(-)
diff --git a/output-eg/nfa_12.v b/output-eg/nfa_12.v
@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 12
+module nfa_12 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output reg match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [4:0] state_reg;
+ wire [4:0] next_state;
+
+ assign next_state[0] = 1'b0;
+ assign next_state[1] = (state_reg[0] && (char_in >= 8'd32) && (char_in <= 8'd126)) | (state_reg[1] && (char_in >= 8'd32) && (char_in <= 8'd126));
+ assign next_state[2] = (state_reg[1] && (char_in == 8'd101));
+ assign next_state[3] = (state_reg[2] && (char_in == 8'd110));
+ assign next_state[4] = (state_reg[3] && (char_in == 8'd100));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted on cycle following end_of_str
+ always @(posedge clk) begin
+ if (rst || start) begin
+ match <= 1'b0;
+ end else if (en) begin
+ if (end_of_str) begin
+ match <= state_reg[4];
+ end else begin
+ match <= 1'b0;
+ end
+ end
+ end
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[4:1];
+
+endmodule
diff --git a/output-eg/nfa_13.v b/output-eg/nfa_13.v
@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 13
+module nfa_13 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output reg match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [3:0] state_reg;
+ wire [3:0] next_state;
+
+ assign next_state[0] = 1'b0;
+ assign next_state[1] = (state_reg[0] && (char_in == 8'd120)) | (state_reg[3] && (char_in == 8'd120));
+ assign next_state[2] = (state_reg[1] && (char_in >= 8'd32) && (char_in <= 8'd126));
+ assign next_state[3] = (state_reg[2] && (char_in == 8'd121));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted on cycle following end_of_str
+ always @(posedge clk) begin
+ if (rst || start) begin
+ match <= 1'b0;
+ end else if (en) begin
+ if (end_of_str) begin
+ match <= state_reg[3];
+ end else begin
+ match <= 1'b0;
+ end
+ end
+ end
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[3:1];
+
+endmodule
diff --git a/output-eg/nfa_14.v b/output-eg/nfa_14.v
@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 14
+module nfa_14 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output reg match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [4:0] state_reg;
+ wire [4:0] next_state;
+
+ assign next_state[0] = 1'b0;
+ assign next_state[1] = (state_reg[0] && (char_in == 8'd97));
+ assign next_state[2] = (state_reg[0] && (char_in == 8'd98));
+ assign next_state[3] = (state_reg[1] && (char_in == 8'd99)) | (state_reg[2] && (char_in == 8'd99));
+ assign next_state[4] = (state_reg[1] && (char_in == 8'd100)) | (state_reg[2] && (char_in == 8'd100));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted on cycle following end_of_str
+ always @(posedge clk) begin
+ if (rst || start) begin
+ match <= 1'b0;
+ end else if (en) begin
+ if (end_of_str) begin
+ match <= (|{state_reg[3], state_reg[4]});
+ end else begin
+ match <= 1'b0;
+ end
+ end
+ end
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[4:1];
+
+endmodule
diff --git a/output-eg/nfa_15.v b/output-eg/nfa_15.v
@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 15
+module nfa_15 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output reg match,
+ output wire active
+);
+
+ // One-hot state register
+ reg [4:0] state_reg;
+ wire [4:0] next_state;
+
+ assign next_state[0] = 1'b0;
+ assign next_state[1] = (state_reg[0] && (char_in == 8'd49));
+ assign next_state[2] = (state_reg[1] && (char_in == 8'd50));
+ assign next_state[3] = (state_reg[2] && (char_in == 8'd51));
+ assign next_state[4] = (state_reg[1] && (char_in == 8'd52)) | (state_reg[3] && (char_in == 8'd52));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted on cycle following end_of_str
+ always @(posedge clk) begin
+ if (rst || start) begin
+ match <= 1'b0;
+ end else if (en) begin
+ if (end_of_str) begin
+ match <= state_reg[4];
+ end else begin
+ match <= 1'b0;
+ end
+ end
+ end
+
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[4:1];
+
+endmodule
diff --git a/output-eg/nfa_2.v b/output-eg/nfa_2.v
@@ -8,7 +8,8 @@ module nfa_2 (
input wire start,
input wire end_of_str,
input wire [7:0] char_in,
- output reg match
+ output reg match,
+ output wire active
);
// One-hot state register
@@ -16,9 +17,9 @@ module nfa_2 (
wire [3:0] next_state;
assign next_state[0] = 1'b0;
- assign next_state[1] = (state_reg[0] && (char_in == 8'd97)) | (state_reg[1] && (char_in == 8'd97)) | (state_reg[2] && (char_in == 8'd97));
- assign next_state[2] = (state_reg[0] && (char_in == 8'd98)) | (state_reg[1] && (char_in == 8'd98)) | (state_reg[2] && (char_in == 8'd98));
- assign next_state[3] = (state_reg[1] && (char_in == 8'd99)) | (state_reg[2] && (char_in == 8'd99));
+ assign next_state[1] = (state_reg[0] && (char_in == 8'd100));
+ assign next_state[2] = (state_reg[1] && (char_in == 8'd111)) | (state_reg[2] && (char_in == 8'd111));
+ assign next_state[3] = (state_reg[1] && (char_in == 8'd103)) | (state_reg[2] && (char_in == 8'd103));
always @(posedge clk) begin
if (rst || start) begin
@@ -35,11 +36,14 @@ module nfa_2 (
match <= 1'b0;
end else if (en) begin
if (end_of_str) begin
- match <= (|{state_reg[1], state_reg[2], state_reg[3]});
+ match <= state_reg[3];
end else begin
match <= 1'b0;
end
end
end
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[3:1];
+
endmodule
diff --git a/output-eg/nfa_3.v b/output-eg/nfa_3.v
@@ -8,7 +8,8 @@ module nfa_3 (
input wire start,
input wire end_of_str,
input wire [7:0] char_in,
- output reg match
+ output reg match,
+ output wire active
);
// One-hot state register
@@ -16,9 +17,9 @@ module nfa_3 (
wire [3:0] next_state;
assign next_state[0] = 1'b0;
- assign next_state[1] = (state_reg[0] && (char_in == 8'd97));
- assign next_state[2] = (state_reg[1] && (char_in >= 8'd32) && (char_in <= 8'd126));
- assign next_state[3] = (state_reg[2] && (char_in == 8'd98));
+ assign next_state[1] = (state_reg[0] && (char_in == 8'd98));
+ assign next_state[2] = (state_reg[1] && (char_in == 8'd101)) | (state_reg[2] && (char_in == 8'd101));
+ assign next_state[3] = (state_reg[2] && (char_in == 8'd112));
always @(posedge clk) begin
if (rst || start) begin
@@ -42,4 +43,7 @@ module nfa_3 (
end
end
+ // Active logic: high if any state other than state 0 is active
+ assign active = |state_reg[3:1];
+
endmodule