xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3// NFA for regex index 3
 4module nfa_3 (
 5    input  wire       clk,
 6    input  wire       en,
 7    input  wire       rst,
 8    input  wire       start,
 9    input  wire       end_of_str,
10    input  wire [7:0] char_in,
11    output reg        match,
12    output wire       active
13);
14
15    // One-hot state register
16    reg [3:0] state_reg;
17    wire [3:0] next_state;
18
19    assign next_state[0] = 1'b0;
20    assign next_state[1] = (state_reg[0] && (char_in == 8'd98));
21    assign next_state[2] = (state_reg[1] && (char_in == 8'd101)) | (state_reg[2] && (char_in == 8'd101));
22    assign next_state[3] = (state_reg[2] && (char_in == 8'd112));
23
24    always @(posedge clk) begin
25        if (rst || start) begin
26            // Reset to start state (one-hot)
27            state_reg <= 1 << 0;
28        end else if (en) begin
29            state_reg <= next_state;
30        end
31    end
32
33    // Match logic: asserted on cycle following end_of_str
34    always @(posedge clk) begin
35        if (rst || start) begin
36            match <= 1'b0;
37        end else if (en) begin
38            if (end_of_str) begin
39                match <= state_reg[3];
40            end else begin
41                match <= 1'b0;
42            end
43        end
44    end
45
46    // Active logic: high if any state other than state 0 is active
47    assign active = |state_reg[3:1];
48
49endmodule