xiiregexbuilder

commit b58127612186e2684a3aa3cb4ebc4574c9926a8c
parent 9d8c9e9dc3de9037f4c6ac2a2c88f8763f4a91c3
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date:   Thu,  2 Apr 2026 04:46:57 +0530

Week 3: Initial Verilog top wrapper and UART TX (Part 2: Core logic)

Diffstat:
M
output-eg/top.v
 | 
16
++++++++++++++++
M
output-eg/uart_tx.v
 | 
36
++++++++++++++++++++++++++++++++++++

2 files changed, 52 insertions(+), 0 deletions(-)
diff --git a/output-eg/top.v b/output-eg/top.v
@@ -10,3 +10,19 @@ module top (
     output wire [5:0] match_bus
 );
 
+    nfa_0 inst_0 (
+        .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[0])
+    );
+
+    nfa_1 inst_1 (
+        .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[1])
+    );
+
+    nfa_2 inst_2 (
+        .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[2])
+    );
+
+    nfa_3 inst_3 (
+        .clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match(match_bus[3])
+    );
+
diff --git a/output-eg/uart_tx.v b/output-eg/uart_tx.v
@@ -25,3 +25,39 @@ module uart_tx #(
         if (rst) begin
             state    <= S_IDLE;
             tx       <= 1'b1;
+            tx_busy  <= 1'b0;
+            clk_cnt  <= 10'd0;
+            bit_idx  <= 3'd0;
+            tx_shift <= 8'd0;
+        end else begin
+            case (state)
+                S_IDLE: begin
+                    tx      <= 1'b1;
+                    tx_busy <= 1'b0;
+                    clk_cnt <= 10'd0;
+                    bit_idx <= 3'd0;
+                    if (tx_start) begin
+                        tx_shift <= tx_data;
+                        tx_busy  <= 1'b1;
+                        state    <= S_START_BIT;
+                    end
+                end
+                S_START_BIT: begin
+                    tx <= 1'b0;
+                    if (clk_cnt < CLKS_PER_BIT - 1)
+                        clk_cnt <= clk_cnt + 1;
+                    else begin
+                        clk_cnt <= 10'd0;
+                        state   <= S_DATA_BITS;
+                    end
+                end
+                S_DATA_BITS: begin
+                    tx <= tx_shift[0];
+                    if (clk_cnt < CLKS_PER_BIT - 1)
+                        clk_cnt <= clk_cnt + 1;
+                    else begin
+                        clk_cnt  <= 10'd0;
+                        tx_shift <= tx_shift >> 1;
+                        if (bit_idx < 7)
+                            bit_idx <= bit_idx + 1;
+                        else begin