commit b1f236bf6138d253c98fb9013a4c7fa20ad9dff2 parent f87bd32015d5f293ce41b5f63d0de69b6805414b Author: Vishrut Gurrala <maydayv7@gmail.com> Date: Fri, 10 Apr 2026 04:00:00 +0530 Week 4: Python Interactive TUI, FPGA Program Scripts, and final verification traces (Part 2: Core logic) Diffstat:
| A | scripts/program.tcl | | | 18 | ++++++++++++++++++ |
1 file changed, 18 insertions(+), 0 deletions(-)
diff --git a/scripts/program.tcl b/scripts/program.tcl @@ -0,0 +1,18 @@ +# VIVADO PROGRAMMING SCRIPT + +open_hw_manager +connect_hw_server +open_hw_target + +# Get first connected FPGA device +set device [lindex [get_hw_devices] 0] +current_hw_device $device +refresh_hw_device -update_hw_probes false $device + +# Set bitstream file and program +# Targeting the bitfile generated by synth.tcl +set_property PROGRAM.FILE "top_fpga.bit" $device +program_hw_devices $device + +# Finish and close +close_hw_manager