xiiregexbuilder

FPGA-Accelerated Regular Expression Matching Engine
commit ac3d5d2f57af85a033baa5ca267312fbdb26b7c7
parent 48a66bfc500eef570ceebbc96de93a37d04adcf0
Author: yash modi <yash3108m@gmail.com>
Date:   Thu,  9 Apr 2026 04:00:00 +0530

Week 4: Emitter optimization simulation verification traces (Part 1: Initial definitions)

Diffstat:
Mdump.vcd | 69+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+), 0 deletions(-)

diff --git a/dump.vcd b/dump.vcd @@ -1425,3 +1425,72 @@ b10 ? #765000 1! +1( +b10 / +b0 0 +b10 2 +b0 3 +b10 5 +b10 8 +b100 9 +b10 ; +b0 < +b10 > + +#770000 +0! +b1111001 & +0( +b1111001 - +b0 6 +b0 ? + +#775000 +1! +1( +b0 / +b0 2 +b0 5 +b100 8 +b0 9 +b0 ; +b0 > + +#780000 +0! +b1100010 & +0( +b1100010 - +b1000 9 + +#785000 +1! +1( +b1000 8 +b0 9 + +#790000 +0! +1% +0( +1, + +#795000 +1! +b1000 ' +1( +17 +b0 8 + +#800000 +0! +0% +0( +0, + +#805000 +1! +b0 ' +1( +07 +