xiiregexbuilder

commit 9d8c9e9dc3de9037f4c6ac2a2c88f8763f4a91c3
parent 4c9186bea3d96f16ab5d8a72d78eb026a8834f94
Author: yash modi <yash3108m@gmail.com>
Date:   Wed,  1 Apr 2026 22:31:18 +0530

Week 3: Implement UART RX hardware FIFO (Part 1: Initial definitions)

Diffstat:
A
output-eg/uart_rx_fifo.v
 | 
15
+++++++++++++++

1 file changed, 15 insertions(+), 0 deletions(-)
diff --git a/output-eg/uart_rx_fifo.v b/output-eg/uart_rx_fifo.v
@@ -0,0 +1,15 @@
+`timescale 1ns / 1ps
+
+
+module uart_rx_fifo #(
+    parameter DEPTH_LOG2 = 4        // depth = 2^DEPTH_LOG2 = 16
+)(
+    input  wire       clk,
+    input  wire       rst,
+    input  wire [7:0] wr_data,
+    input  wire       wr_en,
+    output wire       full,
+    output wire [7:0] rd_data,
+    input  wire       rd_en,
+    output wire       empty
+);