xiiregexbuilder

commit 7ed9849ed122a34e2a44bb3e34c3b217d8f78b41
parent 0785bcad477598ac5904721707a2f2b597020439
Author: yash modi <yash3108m@gmail.com>
Date:   Mon, 23 Mar 2026 23:42:51 +0530

Week 1: Define Verilog Emitter headers (Part 2: Core logic)

Diffstat:
M
src/emitter.h
 | 
23
+++++++++++++++++++++++

1 file changed, 23 insertions(+), 0 deletions(-)
diff --git a/src/emitter.h b/src/emitter.h
@@ -15,3 +15,26 @@ public:
     Emitter() = delete; // Static class, no instances
 
     /**
+     * @brief Emits all Verilog files to the specified directory.
+     * @param nfas           The vector of NFAs to be emitted.
+     * @param outputDir      Directory where files will be written.
+     * @param testStrings    Optional test strings for the testbench.
+     * @param expectedMatches Optional expected match masks for the testbench.
+     */
+    static void emit(const std::vector<std::unique_ptr<NFA>> &nfas,
+                     const std::string &outputDir,
+                     const std::vector<std::string> &testStrings = {},
+                     const std::vector<std::string> &expectedMatches = {});
+
+private:
+    static void emitNFAModule(const NFA &nfa, const std::filesystem::path &outputDir);
+    static void emitTopModule(const std::vector<std::unique_ptr<NFA>> &nfas, const std::filesystem::path &outputDir);
+    static void emitTestbench(const std::vector<std::unique_ptr<NFA>> &nfas,
+                              const std::filesystem::path &outputDir,
+                              const std::vector<std::string> &testStrings,
+                              const std::vector<std::string> &expectedMatches);
+
+    // UART RX receiver
+    static void emitUARTRX(const std::filesystem::path &outputDir);
+
+    // UART TX transmitter