commit 545d26fe1baa8ea075838df67f4e6faad57deb99
parent 1a1bcf8e151fdcf339fd9373f6abddcf1df919f9
Author: Achuthan TM <achuthantm05@gmail.com>
Date: Wed, 8 Apr 2026 10:00:00 +0530
Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 1: Initial definitions)
Diffstat:
| M | dump.vcd | | | 277 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | output-eg/nfa_3.v | | | 45 | +++++++++++++++++++++++++++++++++++++++++++++ |
2 files changed, 322 insertions(+), 0 deletions(-)
diff --git a/dump.vcd b/dump.vcd
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diff --git a/output-eg/nfa_3.v b/output-eg/nfa_3.v
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+
+// NFA for regex index 3
+module nfa_3 (
+ input wire clk,
+ input wire en,
+ input wire rst,
+ input wire start,
+ input wire end_of_str,
+ input wire [7:0] char_in,
+ output reg match
+);
+
+ // One-hot state register
+ reg [3:0] state_reg;
+ wire [3:0] next_state;
+
+ assign next_state[0] = 1'b0;
+ assign next_state[1] = (state_reg[0] && (char_in == 8'd97));
+ assign next_state[2] = (state_reg[1] && (char_in >= 8'd32) && (char_in <= 8'd126));
+ assign next_state[3] = (state_reg[2] && (char_in == 8'd98));
+
+ always @(posedge clk) begin
+ if (rst || start) begin
+ // Reset to start state (one-hot)
+ state_reg <= 1 << 0;
+ end else if (en) begin
+ state_reg <= next_state;
+ end
+ end
+
+ // Match logic: asserted on cycle following end_of_str
+ always @(posedge clk) begin
+ if (rst || start) begin
+ match <= 1'b0;
+ end else if (en) begin
+ if (end_of_str) begin
+ match <= state_reg[3];
+ end else begin
+ match <= 1'b0;
+ end
+ end
+ end
+
+endmodule