xiiregexbuilder

commit 4dec5d9a87d7091515b0a75301dd83e04977e9b5
parent 03a26fc143c8feacc365a73952f3201de6cfd8be
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date:   Sat,  4 Apr 2026 00:36:31 +0530

Week 3: Implement UART RX and partial FPGA top wrapper (Part 1: Initial definitions)

Diffstat:
A
output-eg/top_fpga.v
 | 
49
+++++++++++++++++++++++++++++++++++++++++++++++++
A
output-eg/uart_rx.v
 | 
17
+++++++++++++++++

2 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/output-eg/top_fpga.v b/output-eg/top_fpga.v
@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+
+// =============================================================================
+// top_fpga.v — FPGA Top-Level
+// Regex count: 6
+//
+// Architecture:
+//   uart_rx → uart_rx_fifo → Control FSM → top (NFA engine)
+//                                         → uart_tx → host PC
+//
+// UART response packet (one line per newline received from host):
+//   "MATCH=<6-bit binary> BYTES=<8 hex> HITS=<4 hex per regex,comma-sep>\r\n"
+//
+// Send '?' (0x3F) to query counters without feeding the NFA.
+// =============================================================================
+
+module top_fpga #(
+    parameter NUM_REGEX    = 6,
+    parameter CLKS_PER_BIT = 868   // 100 MHz / 115200 baud
+)(
+    input  wire clk,
+    input  wire rst_btn,
+    input  wire uart_rx_pin,
+    output wire uart_tx_pin,
+    output reg  [5:0] match_leds
+);
+
+    // UART RX
+    wire [7:0] rx_data;
+    wire       rx_ready;
+
+    uart_rx #(.CLKS_PER_BIT(CLKS_PER_BIT)) uart_rx_inst (
+        .clk     (clk),
+        .rx      (uart_rx_pin),
+        .rx_data (rx_data),
+        .rx_ready(rx_ready)
+    );
+
+    // Input FIFO
+    wire [7:0] fifo_rd_data;
+    wire       fifo_empty;
+    wire       fifo_full;
+    reg        fifo_rd_en = 1'b0;
+
+    uart_rx_fifo #(.DEPTH_LOG2(4)) rx_fifo (
+        .clk    (clk),
+        .rst    (rst_btn),
+        .wr_data(rx_data),
+        .wr_en  (rx_ready && !fifo_full),
diff --git a/output-eg/uart_rx.v b/output-eg/uart_rx.v
@@ -0,0 +1,17 @@
+`timescale 1ns / 1ps
+
+
+module uart_rx #(
+    parameter CLKS_PER_BIT = 868 // 100 MHz / 115200 Baud
+)(
+    input  wire       clk,
+    input  wire       rx,
+    output reg  [7:0] rx_data,
+    output reg        rx_ready
+);
+    localparam IDLE = 2'b00, START_BIT = 2'b01, DATA_BITS = 2'b10, STOP_BIT = 2'b11;
+    reg [1:0] state = IDLE;
+    reg [9:0] clk_count = 0;
+    reg [2:0] bit_idx = 0;
+
+    always @(posedge clk) begin