xiiregexbuilder

commit 4c9186bea3d96f16ab5d8a72d78eb026a8834f94
parent 251a9fc87ded97179ef42802e59bea5a992d1352
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date:   Wed,  1 Apr 2026 16:15:39 +0530

Week 3: Initial Verilog top wrapper and UART TX (Part 1: Initial definitions)

Diffstat:
A
output-eg/top.v
 | 
12
++++++++++++
A
output-eg/uart_tx.v
 | 
27
+++++++++++++++++++++++++++

2 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/output-eg/top.v b/output-eg/top.v
@@ -0,0 +1,12 @@
+`timescale 1ns / 1ps
+
+module top (
+    input  wire       clk,
+    input  wire       en,
+    input  wire       rst,
+    input  wire       start,
+    input  wire       end_of_str,
+    input  wire [7:0] char_in,
+    output wire [5:0] match_bus
+);
+
diff --git a/output-eg/uart_tx.v b/output-eg/uart_tx.v
@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+
+
+module uart_tx #(
+    parameter CLKS_PER_BIT = 868   // 100 MHz / 115200 baud
+)(
+    input  wire       clk,
+    input  wire       rst,
+    input  wire [7:0] tx_data,
+    input  wire       tx_start,
+    output reg        tx_busy,
+    output reg        tx
+);
+    localparam S_IDLE      = 3'd0;
+    localparam S_START_BIT = 3'd1;
+    localparam S_DATA_BITS = 3'd2;
+    localparam S_STOP_BIT  = 3'd3;
+
+    reg [2:0]  state    = S_IDLE;
+    reg [9:0]  clk_cnt  = 10'd0;
+    reg [2:0]  bit_idx  = 3'd0;
+    reg [7:0]  tx_shift = 8'd0;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            state    <= S_IDLE;
+            tx       <= 1'b1;