xiiregexbuilder

FPGA-Accelerated Regular Expression Matching Engine
git clone https://github.com/maydayv7/xiiregexbuilder

synth.tcl (973B)

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# VIVADO SYNTHESIS & BITSTREAM SCRIPT
# This script automates the flow for the generated Regex Matcher hardware

# 1. Setup
set part xc7a100tcsg324-1
set outputDir ./build
file mkdir $outputDir

# 2. Create the project in memory
create_project -in_memory -part $part

# 3. Read Verilog files
# All Verilog files listed here are generated by `make run`
read_verilog [glob output/nfa_*.v]
read_verilog output/top.v
read_verilog output/uart_rx.v
read_verilog output/uart_tx.v
read_verilog output/uart_rx_fifo.v
read_verilog output/top_fpga.v

# 4. Read Constraints
read_xdc output/constraints.xdc

# 5. Run Synthesis
synth_design -top top_fpga -part $part

# 6. Run Implementation Flow
opt_design
place_design
route_design

# 7. Generate Reports
report_utilization    -file $outputDir/post_route_util.txt
report_timing_summary -file $outputDir/post_route_timing.txt

# 8. Generate Bitstream
write_bitstream -force $outputDir/top_fpga.bit

# 9. Cleanup and close
close_project