xiiregexbuilder

  1`timescale 1ns / 1ps
  2
  3module uart_rx #(
  4    parameter CLK_FREQ   = 100000000,
  5    parameter BAUD_RATE  = 115200,
  6    parameter FIFO_DEPTH = 16
  7) (
  8    input  wire       clk,
  9    input  wire       rst,
 10    input  wire       rx,
 11    output wire [7:0] data,
 12    output wire       valid,
 13    input  wire       rd_en
 14);
 15  localparam WAIT_LIMIT = CLK_FREQ / BAUD_RATE;
 16
 17  reg [31:0] count = 0;
 18  reg [ 3:0] state = 0;
 19  reg [ 2:0] bit_idx = 0;
 20  reg rx_sync_0, rx_reg;
 21  reg [7:0] rx_byte;
 22  reg       rx_done;
 23
 24  always @(posedge clk) begin
 25    rx_sync_0 <= rx;
 26    rx_reg <= rx_sync_0;
 27  end
 28
 29  // --- UART Receiver State Machine ---
 30  always @(posedge clk) begin
 31    if (rst) begin
 32      state   <= 0;
 33      count   <= 0;
 34      bit_idx <= 0;
 35      rx_done <= 0;
 36    end else begin
 37      rx_done <= 0;
 38      case (state)
 39        0: begin  // Idle
 40          if (rx_reg == 0) begin
 41            if (count < WAIT_LIMIT / 2) count <= count + 1;
 42            else begin
 43              count <= 0;
 44              state <= 1;
 45            end
 46          end else count <= 0;
 47        end
 48        1: begin  // Data Bits
 49          if (count < WAIT_LIMIT - 1) count <= count + 1;
 50          else begin
 51            count <= 0;
 52            rx_byte[bit_idx] <= rx_reg;
 53            if (bit_idx == 7) begin
 54              bit_idx <= 0;
 55              state   <= 2;
 56            end else bit_idx <= bit_idx + 1;
 57          end
 58        end
 59        2: begin  // Stop Bit
 60          if (count < WAIT_LIMIT - 1) count <= count + 1;
 61          else begin
 62            count   <= 0;
 63            rx_done <= 1;
 64            state   <= 0;
 65          end
 66        end
 67        default: state <= 0;
 68      endcase
 69    end
 70  end
 71
 72  // --- Simple Synchronous FIFO ---
 73  localparam ADDR_WIDTH = (FIFO_DEPTH > 1) ? $clog2(FIFO_DEPTH) : 1;
 74  reg [7:0] fifo_mem[0:FIFO_DEPTH-1];
 75  reg [ADDR_WIDTH-1:0] wr_ptr = 0;
 76  reg [ADDR_WIDTH-1:0] rd_ptr = 0;
 77  reg [$clog2(FIFO_DEPTH+1)-1:0] count_fifo = 0;
 78
 79  always @(posedge clk) begin
 80    if (rst) begin
 81      wr_ptr <= 0;
 82      rd_ptr <= 0;
 83      count_fifo <= 0;
 84    end else begin
 85      if (rx_done && count_fifo < FIFO_DEPTH) begin
 86        fifo_mem[wr_ptr] <= rx_byte;
 87        wr_ptr <= wr_ptr + 1;
 88        if (!rd_en) count_fifo <= count_fifo + 1;
 89      end
 90      if (rd_en && count_fifo > 0) begin
 91        rd_ptr <= rd_ptr + 1;
 92        if (!rx_done) count_fifo <= count_fifo - 1;
 93      end
 94    end
 95  end
 96
 97  assign data  = fifo_mem[rd_ptr];
 98  assign valid = (count_fifo > 0);
 99
100endmodule
101
102module uart_tx #(
103    parameter CLK_FREQ  = 100000000,
104    parameter BAUD_RATE = 115200
105) (
106    input  wire       clk,
107    input  wire       rst,
108    input  wire [7:0] data,
109    input  wire       send,
110    output reg        tx = 1,
111    output reg        ready = 1
112);
113  localparam WAIT_LIMIT = CLK_FREQ / BAUD_RATE;
114  reg [31:0] count = 0;
115  reg [ 3:0] state = 0;
116  reg [ 2:0] bit_idx = 0;
117  reg [ 7:0] data_reg;
118
119  always @(posedge clk) begin
120    if (rst) begin
121      state <= 0;
122      tx <= 1;
123      ready <= 1;
124    end else begin
125      case (state)
126        0: begin  // Idle
127          ready <= 1;
128          tx <= 1;
129          if (send) begin
130            data_reg <= data;
131            ready <= 0;
132            tx <= 0;  // Start bit
133            count <= 0;
134            state <= 1;
135          end
136        end
137        1: begin  // Data Bits
138          if (count < WAIT_LIMIT - 1) count <= count + 1;
139          else begin
140            count <= 0;
141            tx <= data_reg[bit_idx];
142            if (bit_idx == 7) begin
143              bit_idx <= 0;
144              state   <= 2;
145            end else bit_idx <= bit_idx + 1;
146          end
147        end
148        2: begin  // Stop Bit
149          if (count < WAIT_LIMIT - 1) count <= count + 1;
150          else begin
151            count <= 0;
152            tx <= 1;
153            state <= 0;
154          end
155        end
156        default: state <= 0;
157      endcase
158    end
159  end
160endmodule