top_fpga.v (5358B)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 | `timescale 1ns / 1ps module top_fpga ( input wire clk, // 100 MHz system clock input wire rst_btn, // Physical reset button input wire uart_rx_pin,// USB UART RX pin output wire uart_tx_pin // USB UART TX pin ); wire [7:0] rx_data; wire rx_ready; uart_rx uart_inst ( .clk(clk), .rx(uart_rx_pin), .rx_data(rx_data), .rx_ready(rx_ready) ); reg nfa_start = 1'b1; reg [7:0] nfa_char_in = 8'h00; reg nfa_en = 1'b0; wire [6:0] match_bus; wire [6:0] active_bus; top regex_engine ( .clk(clk), .en(nfa_en), .rst(rst_btn), .start(nfa_start), .char_in(nfa_char_in), .match_bus(match_bus), .active_bus(active_bus) ); // UART TX Signals reg tx_start = 1'b0; reg [7:0] tx_data = 8'h00; wire tx_busy; uart_tx uart_tx_inst ( .clk(clk), .tx_start(tx_start), .tx_data(tx_data), .tx(uart_tx_pin), .tx_busy(tx_busy) ); // 128-Byte Latency Buffering with Precise Alignment localparam DELAY_LEN = 128; (* ram_style = "distributed" *) reg [7:0] delay_bram [0:DELAY_LEN-1]; reg [6:0] delay_ptr = 0; reg [DELAY_LEN-1:0] commit_history = 0; // Per-NFA Active Histories to isolate redaction contexts reg [DELAY_LEN-1:0] active_history_0 = 0; reg [DELAY_LEN-1:0] active_history_1 = 0; reg [DELAY_LEN-1:0] active_history_2 = 0; reg [DELAY_LEN-1:0] active_history_3 = 0; reg [DELAY_LEN-1:0] active_history_4 = 0; reg [DELAY_LEN-1:0] active_history_5 = 0; reg [DELAY_LEN-1:0] active_history_6 = 0; // Power-On-Reset Initialization reg [7:0] por_count = 0; wire por_rst = (por_count < 8'hFF); reg rx_ready_prev = 0; reg [1:0] step = 0; reg [7:0] rx_latch = 0; always @(posedge clk) begin if (rst_btn || por_rst) begin if (por_count < 8'h80) begin delay_bram[por_count[6:0]] <= 8'h20; // Initialize BRAM sequentially end if (por_count < 8'hFF) por_count <= por_count + 1; nfa_en <= 0; nfa_start <= 1; tx_start <= 0; rx_ready_prev <= 0; delay_ptr <= 0; commit_history <= 0; step <= 0; active_history_0 <= 0; active_history_1 <= 0; active_history_2 <= 0; active_history_3 <= 0; active_history_4 <= 0; active_history_5 <= 0; active_history_6 <= 0; end else begin nfa_start <= 0; nfa_en <= 0; tx_start <= 0; rx_ready_prev <= rx_ready; // Character Processing Sequence if (rx_ready && !rx_ready_prev) begin rx_latch <= rx_data; step <= 1; end case (step) 1: begin // Step 1: Feed NFA Engine nfa_char_in <= rx_latch; nfa_en <= 1; step <= 2; end 2: begin // Step 2: NFA Results and Redaction Output // 1. Read delayed char and check redaction bit (Sampling BEFORE shift) tx_data <= (commit_history[DELAY_LEN-2]) ? 8'h58 : delay_bram[delay_ptr]; tx_start <= 1; // 2. Overwrite slot with new character delay_bram[delay_ptr] <= rx_latch; delay_ptr <= delay_ptr + 1; // 3. Update Histories (Isolating contexts) active_history_0 <= active_bus[0] ? {active_history_0[DELAY_LEN-2:0], 1'b1} : 128'd0; active_history_1 <= active_bus[1] ? {active_history_1[DELAY_LEN-2:0], 1'b1} : 128'd0; active_history_2 <= active_bus[2] ? {active_history_2[DELAY_LEN-2:0], 1'b1} : 128'd0; active_history_3 <= active_bus[3] ? {active_history_3[DELAY_LEN-2:0], 1'b1} : 128'd0; active_history_4 <= active_bus[4] ? {active_history_4[DELAY_LEN-2:0], 1'b1} : 128'd0; active_history_5 <= active_bus[5] ? {active_history_5[DELAY_LEN-2:0], 1'b1} : 128'd0; active_history_6 <= active_bus[6] ? {active_history_6[DELAY_LEN-2:0], 1'b1} : 128'd0; commit_history <= {commit_history[DELAY_LEN-2:0], 1'b0} | (match_bus[0] ? {active_history_0[DELAY_LEN-2:0], 1'b1} : 128'd0) | (match_bus[1] ? {active_history_1[DELAY_LEN-2:0], 1'b1} : 128'd0) | (match_bus[2] ? {active_history_2[DELAY_LEN-2:0], 1'b1} : 128'd0) | (match_bus[3] ? {active_history_3[DELAY_LEN-2:0], 1'b1} : 128'd0) | (match_bus[4] ? {active_history_4[DELAY_LEN-2:0], 1'b1} : 128'd0) | (match_bus[5] ? {active_history_5[DELAY_LEN-2:0], 1'b1} : 128'd0) | (match_bus[6] ? {active_history_6[DELAY_LEN-2:0], 1'b1} : 128'd0); step <= 0; end endcase end end endmodule |