xiiregexbuilder
FPGA-Accelerated Regular Expression Matching Engineoutput-pii/nfa_0.v (2216B)
1`timescale 1ns / 1ps
2
3// NFA for regex index 0
4module nfa_0 (
5 input wire clk,
6 input wire en,
7 input wire rst,
8 input wire start,
9 input wire end_of_str,
10 input wire [7:0] char_in,
11 output wire match,
12 output wire active
13);
14
15 // One-hot state register
16 reg [5:0] state_reg;
17 wire [5:0] next_state;
18
19 assign next_state[0] = 1'b1;
20 assign next_state[1] = (state_reg[0] && (char_in == 8'd46)) | (state_reg[0] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[0] && (char_in >= 8'd65) && (char_in <= 8'd90)) | (state_reg[0] && (char_in >= 8'd97) && (char_in <= 8'd122)) | (state_reg[1] && (char_in == 8'd46)) | (state_reg[1] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[1] && (char_in >= 8'd65) && (char_in <= 8'd90)) | (state_reg[1] && (char_in >= 8'd97) && (char_in <= 8'd122));
21 assign next_state[2] = (state_reg[1] && (char_in == 8'd64));
22 assign next_state[3] = (state_reg[2] && (char_in == 8'd46)) | (state_reg[2] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[2] && (char_in >= 8'd65) && (char_in <= 8'd90)) | (state_reg[2] && (char_in >= 8'd97) && (char_in <= 8'd122)) | (state_reg[3] && (char_in == 8'd46)) | (state_reg[3] && (char_in >= 8'd48) && (char_in <= 8'd57)) | (state_reg[3] && (char_in >= 8'd65) && (char_in <= 8'd90)) | (state_reg[3] && (char_in >= 8'd97) && (char_in <= 8'd122));
23 assign next_state[4] = (state_reg[3] && (char_in == 8'd46));
24 assign next_state[5] = (state_reg[4] && (char_in >= 8'd65) && (char_in <= 8'd90)) | (state_reg[4] && (char_in >= 8'd97) && (char_in <= 8'd122)) | (state_reg[5] && (char_in >= 8'd65) && (char_in <= 8'd90)) | (state_reg[5] && (char_in >= 8'd97) && (char_in <= 8'd122));
25
26 always @(posedge clk) begin
27 if (rst || start) begin
28 // Reset to start state (one-hot)
29 state_reg <= 1 << 0;
30 end else if (en) begin
31 state_reg <= next_state;
32 end
33 end
34
35 // Match logic: asserted immediately on accept state (combinational)
36 assign match = state_reg[5];
37
38 // Active logic: high if any state other than state 0 is active
39 assign active = |state_reg[5:1];
40
41endmodule