xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3// NFA for regex index 9
 4module nfa_9 (
 5    input  wire       clk,
 6    input  wire       en,
 7    input  wire       rst,
 8    input  wire       start,
 9    input  wire       end_of_str,
10    input  wire [7:0] char_in,
11    output reg        match,
12    output wire       active
13);
14
15    // One-hot state register
16    reg [5:0] state_reg;
17    wire [5:0] next_state;
18
19    assign next_state[0] = 1'b0;
20    assign next_state[1] = (state_reg[0] && (char_in == 8'd104));
21    assign next_state[2] = (state_reg[1] && (char_in == 8'd101));
22    assign next_state[3] = (state_reg[0] && (char_in == 8'd108)) | (state_reg[2] && (char_in == 8'd108));
23    assign next_state[4] = (state_reg[3] && (char_in == 8'd108));
24    assign next_state[5] = (state_reg[4] && (char_in == 8'd111));
25
26    always @(posedge clk) begin
27        if (rst || start) begin
28            // Reset to start state (one-hot)
29            state_reg <= 1 << 0;
30        end else if (en) begin
31            state_reg <= next_state;
32        end
33    end
34
35    // Match logic: asserted on cycle following end_of_str
36    always @(posedge clk) begin
37        if (rst || start) begin
38            match <= 1'b0;
39        end else if (en) begin
40            if (end_of_str) begin
41                match <= state_reg[5];
42            end else begin
43                match <= 1'b0;
44            end
45        end
46    end
47
48    // Active logic: high if any state other than state 0 is active
49    assign active = |state_reg[5:1];
50
51endmodule