xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3// NFA for regex index 6
 4module nfa_6 (
 5    input  wire       clk,
 6    input  wire       en,
 7    input  wire       rst,
 8    input  wire       start,
 9    input  wire       end_of_str,
10    input  wire [7:0] char_in,
11    output reg        match,
12    output wire       active
13);
14
15    // One-hot state register
16    reg [10:0] state_reg;
17    wire [10:0] next_state;
18
19    assign next_state[0] = 1'b0;
20    assign next_state[1] = (state_reg[0] && (char_in == 8'd114));
21    assign next_state[2] = (state_reg[1] && (char_in == 8'd101));
22    assign next_state[3] = (state_reg[2] && (char_in == 8'd100));
23    assign next_state[4] = (state_reg[0] && (char_in == 8'd98));
24    assign next_state[5] = (state_reg[4] && (char_in == 8'd108));
25    assign next_state[6] = (state_reg[5] && (char_in == 8'd117));
26    assign next_state[7] = (state_reg[6] && (char_in == 8'd101));
27    assign next_state[8] = (state_reg[3] && (char_in == 8'd99)) | (state_reg[7] && (char_in == 8'd99));
28    assign next_state[9] = (state_reg[8] && (char_in == 8'd97));
29    assign next_state[10] = (state_reg[9] && (char_in == 8'd114));
30
31    always @(posedge clk) begin
32        if (rst || start) begin
33            // Reset to start state (one-hot)
34            state_reg <= 1 << 0;
35        end else if (en) begin
36            state_reg <= next_state;
37        end
38    end
39
40    // Match logic: asserted on cycle following end_of_str
41    always @(posedge clk) begin
42        if (rst || start) begin
43            match <= 1'b0;
44        end else if (en) begin
45            if (end_of_str) begin
46                match <= state_reg[10];
47            end else begin
48                match <= 1'b0;
49            end
50        end
51    end
52
53    // Active logic: high if any state other than state 0 is active
54    assign active = |state_reg[10:1];
55
56endmodule