xiiregexbuilder

 1`timescale 1ns / 1ps
 2
 3// NFA for regex index 10
 4module nfa_10 (
 5    input  wire       clk,
 6    input  wire       en,
 7    input  wire       rst,
 8    input  wire       start,
 9    input  wire       end_of_str,
10    input  wire [7:0] char_in,
11    output reg        match,
12    output wire       active
13);
14
15    // One-hot state register
16    reg [4:0] state_reg;
17    wire [4:0] next_state;
18
19    assign next_state[0] = 1'b0;
20    assign next_state[1] = (state_reg[0] && (char_in == 8'd97));
21    assign next_state[2] = (state_reg[1] && (char_in == 8'd98)) | (state_reg[2] && (char_in == 8'd98)) | (state_reg[3] && (char_in == 8'd98));
22    assign next_state[3] = (state_reg[1] && (char_in == 8'd99)) | (state_reg[2] && (char_in == 8'd99)) | (state_reg[3] && (char_in == 8'd99));
23    assign next_state[4] = (state_reg[1] && (char_in == 8'd100)) | (state_reg[2] && (char_in == 8'd100)) | (state_reg[3] && (char_in == 8'd100));
24
25    always @(posedge clk) begin
26        if (rst || start) begin
27            // Reset to start state (one-hot)
28            state_reg <= 1 << 0;
29        end else if (en) begin
30            state_reg <= next_state;
31        end
32    end
33
34    // Match logic: asserted on cycle following end_of_str
35    always @(posedge clk) begin
36        if (rst || start) begin
37            match <= 1'b0;
38        end else if (en) begin
39            if (end_of_str) begin
40                match <= state_reg[4];
41            end else begin
42                match <= 1'b0;
43            end
44        end
45    end
46
47    // Active logic: high if any state other than state 0 is active
48    assign active = |state_reg[4:1];
49
50endmodule