xiiregexbuilder

  1################################
  2# Makefile for XIIRegexBuilder #
  3################################
  4
  5# OS Detection
  6ifeq ($(OS),Windows_NT)
  7    EXE := .exe
  8    RM := del /f /q
  9    RMDIR := rmdir /s /q
 10    MKDIR = if not exist $(subst /,\,$1) mkdir $(subst /,\,$1)
 11    FIX_PATH = $(subst /,\,$1)
 12else
 13    EXE :=
 14    RM := rm -f
 15    RMDIR := rm -rf
 16    MKDIR = mkdir -p $1
 17    FIX_PATH = $1
 18endif
 19
 20CC = g++
 21CFLAGS = -Wall -Wextra -std=c++17 -Isrc -static
 22BUILD_DIR = build
 23TARGET = $(BUILD_DIR)/regex_builder$(EXE)
 24TESTER = $(BUILD_DIR)/nfa_tester$(EXE)
 25GOLDEN = $(BUILD_DIR)/golden$(EXE)
 26SRCS = src/main.cpp src/lexer.cpp src/parser.cpp src/nfa.cpp src/emitter.cpp
 27TEST_SRCS = src/parser_tester.cpp src/lexer.cpp src/parser.cpp src/nfa.cpp
 28GOLDEN_SRCS = src/golden.cpp
 29OBJS = $(SRCS:.cpp=.o)
 30TEST_OBJS = $(TEST_SRCS:.cpp=.o)
 31GOLDEN_OBJS = $(GOLDEN_SRCS:.cpp=.o)
 32
 33INPUT_DIR = inputs
 34OUTPUT_DIR = output
 35
 36# Vivado Simulation Tools
 37VIVADO_PATH = vivado
 38XVLOG = xvlog
 39XELAB = xelab
 40XSIM  = xsim
 41SIM_TOP = tb_top
 42SNAPSHOT = regex_sim
 43
 44# Processor variables
 45PROC_BUILD_DIR = processor/build
 46PROC_SRC_DIR = processor
 47PROC_PY_DIR = processor/src
 48
 49$(TARGET): $(OBJS) | $(BUILD_DIR)
 50	$(CC) $(CFLAGS) -o $(TARGET) $(OBJS)
 51
 52$(TESTER): $(TEST_OBJS) | $(BUILD_DIR)
 53	$(CC) $(CFLAGS) -o $(TESTER) $(TEST_OBJS)
 54
 55$(GOLDEN): $(GOLDEN_OBJS) | $(BUILD_DIR)
 56	$(CC) $(CFLAGS) -o $(GOLDEN) $(GOLDEN_OBJS)
 57
 58$(BUILD_DIR):
 59	$(call MKDIR,$(BUILD_DIR))
 60
 61$(PROC_BUILD_DIR):
 62	$(call MKDIR,$(PROC_BUILD_DIR))
 63
 64$(OUTPUT_DIR):
 65	$(call MKDIR,$(OUTPUT_DIR))
 66
 67%.o: %.cpp
 68	$(CC) $(CFLAGS) -c $< -o $@
 69
 70all: $(TARGET) $(GOLDEN)
 71
 72run: all | $(OUTPUT_DIR)
 73	$(TARGET) $(INPUT_DIR)/regexes.txt $(INPUT_DIR)/test_strings.txt $(OUTPUT_DIR)
 74
 75test: $(TESTER)
 76	$(TESTER) $(INPUT_DIR)/regexes.txt $(INPUT_DIR)/test_strings.txt
 77
 78golden: $(GOLDEN) | $(OUTPUT_DIR)
 79	$(GOLDEN) $(INPUT_DIR)/regexes.txt $(INPUT_DIR)/test_strings.txt $(OUTPUT_DIR)/expected_matches.txt
 80
 81sim: run
 82	@echo "1. Compiling Verilog files..."
 83	$(XVLOG) $(OUTPUT_DIR)/*.v 
 84	@echo "2. Elaborating design..."
 85	$(XELAB) -top $(SIM_TOP) -snapshot $(SNAPSHOT) -debug typical
 86	@echo "3. Running simulation..."
 87	$(XSIM) $(SNAPSHOT) -R
 88
 89# FPGA Targets
 90BITSTREAM ?= build/top_fpga.bit
 91
 92synth: run
 93	@echo "Launching Vivado Synthesis Flow..."
 94	$(VIVADO_PATH) -mode batch -source $(call FIX_PATH,scripts/synth.tcl)
 95
 96program:
 97	@echo "Launching Vivado Programming Flow for $(BITSTREAM)..."
 98	$(VIVADO_PATH) -mode batch -source $(call FIX_PATH,scripts/program.tcl) -tclargs $(BITSTREAM)
 99
100# Processor Targets
101proc_asm: | $(PROC_BUILD_DIR)
102	python $(PROC_PY_DIR)/compile_regex.py $(PROC_SRC_DIR)/regex.txt $(PROC_BUILD_DIR)/regexes.rasm
103	python $(PROC_PY_DIR)/asm.py $(PROC_BUILD_DIR)/regexes.rasm $(PROC_BUILD_DIR)/imem.hex
104
105proc_sim: proc_asm
106	@echo "1. Compiling Verilog files for Processor..."
107	$(XVLOG) -work work $(PROC_SRC_DIR)/regex_cpu.v $(PROC_SRC_DIR)/tb_regex_cpu.v
108	@echo "2. Elaborating design..."
109	$(XELAB) -top tb_regex_cpu -snapshot cpu_sim -debug typical
110	@echo "3. Running simulation..."
111	$(XSIM) cpu_sim -R
112
113proc_update_regex: | $(PROC_BUILD_DIR)
114	python $(PROC_PY_DIR)/compile_regex.py $(PROC_SRC_DIR)/regex.txt $(PROC_BUILD_DIR)/regexes.rasm
115	python $(PROC_PY_DIR)/asm.py $(PROC_BUILD_DIR)/regexes.rasm $(PROC_BUILD_DIR)/imem.hex
116	python $(PROC_PY_DIR)/prog_fpga.py $(PROC_BUILD_DIR)/imem.hex
117
118proc_synth: proc_asm | $(PROC_BUILD_DIR)
119	@echo "Launching Vivado Synthesis Flow for Processor..."
120	$(VIVADO_PATH) -mode batch -source $(call FIX_PATH,scripts/synth_proc.tcl)
121
122proc_program:
123	$(MAKE) program BITSTREAM=$(PROC_BUILD_DIR)/top_fpga.bit
124
125# PII Guard Targets
126pii_build: all | $(OUTPUT_DIR)
127	$(TARGET) --pii pii/pii_regexes.txt $(INPUT_DIR)/test_strings.txt $(OUTPUT_DIR)
128
129pii_synth: pii_build
130	@echo "Launching Vivado Synthesis Flow for PII Guard..."
131	$(VIVADO_PATH) -mode batch -source $(call FIX_PATH,scripts/synth_pii.tcl)
132
133clean:
134	-$(RM) $(call FIX_PATH,src/*.o)
135	-$(RMDIR) $(call FIX_PATH,$(BUILD_DIR))
136	-$(RMDIR) $(call FIX_PATH,$(OUTPUT_DIR))
137	-$(RMDIR) $(call FIX_PATH,processor/build)
138	-$(RM) *.bit *.log *.jou *.pb *.wdb *.str usage_statistics_webtalk.*
139	-$(RM) clockInfo.txt dfx_runtime.txt *.hex *.exe
140	-$(RMDIR) xsim.dir .Xil
141
142.PHONY: all run test golden synth program proc_asm proc_sim proc_update_regex proc_synth proc_program pii_build pii_synth clean