xiiregexbuilder

FPGA-Accelerated Regular Expression Matching Engine
commit f402b6ca0c8cb2ab86e3152f91e1e9e67cf7fc48
parent d6c34c118cad55b182f2398bc451bea15ba31a95
Author: yash modi <yash3108m@gmail.com>
Date:   Thu,  9 Apr 2026 16:00:00 +0530

Week 4: Emitter optimization simulation verification traces (Part 3: Finalizing)

Diffstat:
Mdump.vcd | 49+++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+), 0 deletions(-)

diff --git a/dump.vcd b/dump.vcd @@ -1588,3 +1588,52 @@ b101001 - 0! 0% 0( +0, + +#885000 +1! +1( + +#890000 +0! +1$ +0( +1+ + +#895000 +1! +1( +b1 / +b1 2 +b1 5 +b1 8 +b1 ; +b1 > + +#900000 +0! +0$ +b1100001 & +0( +0+ +b1100001 - +b10 0 +b10 3 +b10 6 +b10 9 +b10 < +b10 ? + +#905000 +1! +1( +b10 / +b0 0 +b10 2 +b0 3 +b10 5 +b10 8 +b100 9 +b10 ; +b0 < +b10 >