xiiregexbuilder

commit e92ed1cba89830230f45d2f0afe7aa7c32cdeb58
parent 0353a880c810bf5fb33dd5633bb11a14f488ecec
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date:   Sun,  5 Apr 2026 14:10:26 +0530

Week 3: Implement UART RX and partial FPGA top wrapper (Part 3: Finalizing)

Diffstat:
M
output-eg/top_fpga.v
 | 
35
+++++++++++++++++++++++++++++++++++
M
output-eg/uart_rx.v
 | 
13
+++++++++++++

2 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/output-eg/top_fpga.v b/output-eg/top_fpga.v
@@ -113,3 +113,38 @@ module top_fpga #(
 
     always @(posedge clk) begin
         tx_start_r <= 1'b0;
+        if (rst_btn) begin
+            tx_state <= TX_IDLE;
+            tx_ptr   <= 7'd0;
+        end else begin
+            case (tx_state)
+                TX_IDLE: if (tx_send) begin tx_ptr <= 7'd0; tx_state <= TX_LOAD; end
+                TX_LOAD: if (!tx_busy) begin
+                    tx_data_r  <= tx_buf[tx_ptr];
+                    tx_start_r <= 1'b1;
+                    tx_state   <= TX_WAIT;
+                end
+                TX_WAIT: if (tx_busy)  tx_state <= TX_NEXT;
+                TX_NEXT: if (!tx_busy) begin
+                    if (tx_ptr + 1 < tx_len) begin
+                        tx_ptr   <= tx_ptr + 1;
+                        tx_state <= TX_LOAD;
+                    end else
+                        tx_state <= TX_IDLE;
+                end
+            endcase
+        end
+    end
+
+    // build_response Task
+    // Fills tx_buf with the ASCII response packet in one clock cycle.
+    // Format: "MATCH=<bits> BYTES=<8hex> HITS=<4hex per regex,csv>\r\n"
+    reg [6:0]  bp;         // build pointer (local to task scope)
+    reg [15:0] tmp16;
+    integer    ri;
+
+    task build_response;
+        input [5:0] mbits;
+        input [31:0]          bcount;
+        integer k;
+        begin : build_task
diff --git a/output-eg/uart_rx.v b/output-eg/uart_rx.v
@@ -38,3 +38,16 @@ module uart_rx #(
                     rx_data[bit_idx] <= rx;
                     if (bit_idx < 7) bit_idx <= bit_idx + 1;
                     else state <= STOP_BIT;
+                end
+            end
+            STOP_BIT: begin
+                if (clk_count < CLKS_PER_BIT-1) begin
+                    clk_count <= clk_count + 1;
+                end else begin
+                    if (rx == 1'b1) rx_ready <= 1'b1;
+                    state <= IDLE;
+                end
+            end
+        endcase
+    end
+endmodule