xiiregexbuilder

commit e61f0c4cb1f16d469d7c21c58ac1c967dc7a69a8
parent cb0d9aba0f8b2d5d8f2a43d17c2eb32c51ef9fa3
Author: RahulSannapureddy <rahul.sannapureddy@gmail.com>
Date:   Mon, 30 Mar 2026 10:55:23 +0530

Week 2: Add Makefile for build automation (Part 3: Finalizing)

Diffstat:
M
Makefile
 | 
23
+++++++++++++++++++++++

1 file changed, 23 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -75,3 +75,26 @@ sim: run
 	@echo "1. Compiling Verilog files..."
 	$(XVLOG) $(OUTPUT_DIR)/*.v 
 	@echo "2. Elaborating design..."
+	$(XELAB) -top $(SIM_TOP) -snapshot $(SNAPSHOT) -debug typical
+	@echo "3. Running simulation..."
+	$(XSIM) $(SNAPSHOT) -R
+
+# FPGA Targets
+synth: run
+	@echo "Launching Vivado Synthesis Flow..."
+	$(VIVADO_PATH) -mode batch -source $(call FIX_PATH,scripts/synth.tcl)
+
+program:
+	@echo "Launching Vivado Programming Flow..."
+	$(VIVADO_PATH) -mode batch -source $(call FIX_PATH,scripts/program.tcl)
+
+
+clean:
+	-$(RM) $(call FIX_PATH,src/*.o)
+	-$(RMDIR) $(call FIX_PATH,$(BUILD_DIR))
+	-$(RMDIR) $(call FIX_PATH,$(OUTPUT_DIR))
+	-$(RM) *.bit *.log *.jou *.pb *.wdb *.str usage_statistics_webtalk.*
+	-$(RM) clockInfo.txt dfx_runtime.txt
+	-$(RMDIR) xsim.dir .Xil
+
+.PHONY: all run test golden clean