xiiregexbuilder

FPGA-Accelerated Regular Expression Matching Engine
commit d1b99d1b6e876814a909ca047abe1eff3daddd37
parent 4b3f38e1350bacc56bb8910fa29785a0a77df3d2
Author: Pranav Prabhu Kumble <kumblepranavprabhu@gmail.com>
Date:   Mon,  6 Apr 2026 15:13:02 +0530

Week 3: Full hardware verification simulation traces (Part 2: Core logic)

Diffstat:
Mdump.vcd | 201+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 201 insertions(+), 0 deletions(-)

diff --git a/dump.vcd b/dump.vcd @@ -843,3 +843,204 @@ b100 ; b0 < b100 > +#390000 +0! +0( + +#395000 +1! +1( +b1000 8 +b0 9 +b0 ; + +#400000 +0! +b1100011 & +0( +b1100011 - +b1000 3 +b1000 6 +b1000 ? + +#405000 +1! +1( +b1000 2 +b0 3 +b1000 5 +b0 6 +b0 8 +b1000 > +b0 ? + +#410000 +0! +1% +0( +1, + +#415000 +1! +b110 ' +1( +11 +b0 2 +14 +b0 5 +b0 > + +#420000 +0! +0% +0( +0, + +#425000 +1! +b0 ' +1( +01 +04 + +#430000 +0! +1$ +0( +1+ + +#435000 +1! +1( +b1 / +b1 2 +b1 5 +b1 8 +b1 ; +b1 > +b1000 ? + +#440000 +0! +0$ +b1100001 & +0( +0+ +b1100001 - +b10 0 +b10 3 +b10 6 +b10 9 +b10 < +b10 ? + +#445000 +1! +1( +b10 / +b0 0 +b10 2 +b0 3 +b10 5 +b10 8 +b100 9 +b10 ; +b0 < +b10 > + +#450000 +0! +b1100010 & +0( +b1100010 - +b100 3 +b100 6 +b100 < +b100 ? + +#455000 +1! +1( +b0 / +b100 2 +b100 5 +b100 8 +b1000 9 +b100 ; +b0 < +b100 > + +#460000 +0! +0( + +#465000 +1! +1( +b1000 8 +b0 9 +b0 ; + +#470000 +0! +0( + +#475000 +1! +1( +b0 8 + +#480000 +0! +b1100011 & +0( +b1100011 - +b1000 3 +b1000 6 +b1000 ? + +#485000 +1! +1( +b1000 2 +b0 3 +b1000 5 +b0 6 +b1000 > +b0 ? + +#490000 +0! +1% +0( +1, + +#495000 +1! +b110 ' +1( +11 +b0 2 +14 +b0 5 +b0 > + +#500000 +0! +0% +0( +0, + +#505000 +1! +b0 ' +1( +01 +04 + +#510000 +0! +1$ +0( +1+ +