xiiregexbuilder

FPGA-Accelerated Regular Expression Matching Engine
commit 89aad7f8fe7a89f038f0d28e4f20d0d39c0bcf19
parent 89d79be69ad02a0e9f5a249e9fc93f5a2738dfec
Author: Pranav Prabhu Kumble <kumblepranavprabhu@gmail.com>
Date:   Mon,  6 Apr 2026 02:41:44 +0530

Week 3: Full hardware verification simulation traces (Part 1: Initial definitions)

Diffstat:
Mdump.vcd | 150+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+), 0 deletions(-)

diff --git a/dump.vcd b/dump.vcd @@ -693,3 +693,153 @@ b10 2 b0 3 b10 5 b10 8 +b100 9 +b10 ; +b0 < +b10 > + +#320000 +0! +b1100010 & +0( +b1100010 - +b100 3 +b100 6 +b100 < +b100 ? + +#325000 +1! +1( +b0 / +b100 2 +b100 5 +b100 8 +b1000 9 +b100 ; +b0 < +b100 > + +#330000 +0! +b1100011 & +0( +b1100011 - +b1000 3 +b1000 6 +b0 9 +b1000 < +b1000 ? + +#335000 +1! +1( +b1000 2 +b0 3 +b1000 5 +b0 6 +b0 8 +b1000 ; +b0 < +b1000 > +b0 ? + +#340000 +0! +1% +0( +1, + +#345000 +1! +b10110 ' +1( +11 +b0 2 +14 +b0 5 +1: +b0 ; +b0 > + +#350000 +0! +0% +0( +0, + +#355000 +1! +b0 ' +1( +01 +04 +0: + +#360000 +0! +1$ +0( +1+ + +#365000 +1! +1( +b1 / +b1 2 +b1 5 +b1 8 +b1 ; +b1 > +b1000 ? + +#370000 +0! +0$ +b1100001 & +0( +0+ +b1100001 - +b10 0 +b10 3 +b10 6 +b10 9 +b10 < +b10 ? + +#375000 +1! +1( +b10 / +b0 0 +b10 2 +b0 3 +b10 5 +b10 8 +b100 9 +b10 ; +b0 < +b10 > + +#380000 +0! +b1100010 & +0( +b1100010 - +b100 3 +b100 6 +b100 < +b100 ? + +#385000 +1! +1( +b0 / +b100 2 +b100 5 +b100 8 +b1000 9 +b100 ; +b0 < +b100 > +