commit 251a9fc87ded97179ef42802e59bea5a992d1352
parent 3bc50cb168985a7a7599fd9983ef1956e0c829c8
Author: RahulSannapureddy <rahul.sannapureddy@gmail.com>
Date: Wed, 1 Apr 2026 10:00:00 +0530
Week 3: Implement Top Testbench and start simulation logging (Part 1: Initial definitions)
Diffstat:
| A | dump.vcd | | | 99 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | output-eg/tb_top.v | | | 91 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
2 files changed, 190 insertions(+), 0 deletions(-)
diff --git a/dump.vcd b/dump.vcd
@@ -0,0 +1,99 @@
+$date
+ Tue Mar 31 10:02:33 2026
+$end
+
+$version
+ 2025.2
+ $dumpfile ("dump.vcd")
+$end
+
+$timescale
+ 1ps
+$end
+
+$scope module tb_top $end
+$var reg 1 ! clk $end
+$var reg 1 " en $end
+$var reg 1 # rst $end
+$var reg 1 $ start $end
+$var reg 1 % end_of_str $end
+$var reg 8 & char_in [7:0] $end
+$var wire 6 ' match_bus [5:0] $end
+$scope module uut $end
+$var wire 1 ( clk $end
+$var wire 1 ) en $end
+$var wire 1 * rst $end
+$var wire 1 + start $end
+$var wire 1 , end_of_str $end
+$var wire 8 - char_in [7:0] $end
+$var wire 6 ' match_bus [5:0] $end
+$scope module inst_0 $end
+$var wire 1 ( clk $end
+$var wire 1 ) en $end
+$var wire 1 * rst $end
+$var wire 1 + start $end
+$var wire 1 , end_of_str $end
+$var wire 8 - char_in [7:0] $end
+$var reg 1 . match $end
+$var reg 3 / state_reg [2:0] $end
+$var wire 3 0 next_state [2:0] $end
+$upscope $end
+$scope module inst_1 $end
+$var wire 1 ( clk $end
+$var wire 1 ) en $end
+$var wire 1 * rst $end
+$var wire 1 + start $end
+$var wire 1 , end_of_str $end
+$var wire 8 - char_in [7:0] $end
+$var reg 1 1 match $end
+$var reg 4 2 state_reg [3:0] $end
+$var wire 4 3 next_state [3:0] $end
+$upscope $end
+$scope module inst_2 $end
+$var wire 1 ( clk $end
+$var wire 1 ) en $end
+$var wire 1 * rst $end
+$var wire 1 + start $end
+$var wire 1 , end_of_str $end
+$var wire 8 - char_in [7:0] $end
+$var reg 1 4 match $end
+$var reg 4 5 state_reg [3:0] $end
+$var wire 4 6 next_state [3:0] $end
+$upscope $end
+$scope module inst_3 $end
+$var wire 1 ( clk $end
+$var wire 1 ) en $end
+$var wire 1 * rst $end
+$var wire 1 + start $end
+$var wire 1 , end_of_str $end
+$var wire 8 - char_in [7:0] $end
+$var reg 1 7 match $end
+$var reg 4 8 state_reg [3:0] $end
+$var wire 4 9 next_state [3:0] $end
+$upscope $end
+$scope module inst_4 $end
+$var wire 1 ( clk $end
+$var wire 1 ) en $end
+$var wire 1 * rst $end
+$var wire 1 + start $end
+$var wire 1 , end_of_str $end
+$var wire 8 - char_in [7:0] $end
+$var reg 1 : match $end
+$var reg 4 ; state_reg [3:0] $end
+$var wire 4 < next_state [3:0] $end
+$upscope $end
+$scope module inst_5 $end
+$var wire 1 ( clk $end
+$var wire 1 ) en $end
+$var wire 1 * rst $end
+$var wire 1 + start $end
+$var wire 1 , end_of_str $end
+$var wire 8 - char_in [7:0] $end
+$var reg 1 = match $end
+$var reg 6 > state_reg [5:0] $end
+$var wire 6 ? next_state [5:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+
diff --git a/output-eg/tb_top.v b/output-eg/tb_top.v
@@ -0,0 +1,91 @@
+`timescale 1ns / 1ps
+
+module tb_top;
+ reg clk, en, rst, start, end_of_str;
+ reg [7:0] char_in;
+ wire [5:0] match_bus;
+
+ top uut (.clk(clk), .en(en), .rst(rst), .start(start), .end_of_str(end_of_str), .char_in(char_in), .match_bus(match_bus));
+
+ always #5 clk = ~clk;
+
+ initial begin
+ // synthesis translate_off
+ `ifndef SYNTHESIS
+ $dumpfile("dump.vcd");
+ $dumpvars(0, tb_top);
+ `endif
+ // synthesis translate_on
+
+ clk = 0; en = 1; rst = 1; start = 0; end_of_str = 0; char_in = 0;
+ #20 rst = 0; #10;
+
+ // Test case 0: "a"
+ start = 1; #10 start = 0;
+ char_in = 8'h61; #10;
+ end_of_str = 1; #10;
+ // Match output is valid on the cycle immediately following end_of_str assertion
+ if (match_bus === 6'b000101) begin
+ $display("PASS: Test case 0 ('a') matches expected mask 000101");
+ end else begin
+ $display("FAIL: Test case 0 ('a') expected 000101, got %b", match_bus);
+ end
+ end_of_str = 0; #10;
+
+ // Test case 1: "b"
+ start = 1; #10 start = 0;
+ char_in = 8'h62; #10;
+ end_of_str = 1; #10;
+ // Match output is valid on the cycle immediately following end_of_str assertion
+ if (match_bus === 6'b000101) begin
+ $display("PASS: Test case 1 ('b') matches expected mask 000101");
+ end else begin
+ $display("FAIL: Test case 1 ('b') expected 000101, got %b", match_bus);
+ end
+ end_of_str = 0; #10;
+
+ // Test case 2: "c"
+ start = 1; #10 start = 0;
+ char_in = 8'h63; #10;
+ end_of_str = 1; #10;
+ // Match output is valid on the cycle immediately following end_of_str assertion
+ if (match_bus === 6'b000000) begin
+ $display("PASS: Test case 2 ('c') matches expected mask 000000");
+ end else begin
+ $display("FAIL: Test case 2 ('c') expected 000000, got %b", match_bus);
+ end
+ end_of_str = 0; #10;
+
+ // Test case 3: "aa"
+ start = 1; #10 start = 0;
+ char_in = 8'h61; #10;
+ char_in = 8'h61; #10;
+ end_of_str = 1; #10;
+ // Match output is valid on the cycle immediately following end_of_str assertion
+ if (match_bus === 6'b000100) begin
+ $display("PASS: Test case 3 ('aa') matches expected mask 000100");
+ end else begin
+ $display("FAIL: Test case 3 ('aa') expected 000100, got %b", match_bus);
+ end
+ end_of_str = 0; #10;
+
+ // Test case 4: "ab"
+ start = 1; #10 start = 0;
+ char_in = 8'h61; #10;
+ char_in = 8'h62; #10;
+ end_of_str = 1; #10;
+ // Match output is valid on the cycle immediately following end_of_str assertion
+ if (match_bus === 6'b000100) begin
+ $display("PASS: Test case 4 ('ab') matches expected mask 000100");
+ end else begin
+ $display("FAIL: Test case 4 ('ab') expected 000100, got %b", match_bus);
+ end
+ end_of_str = 0; #10;
+
+ // Test case 5: "ac"
+ start = 1; #10 start = 0;
+ char_in = 8'h61; #10;
+ char_in = 8'h63; #10;
+ end_of_str = 1; #10;
+ // Match output is valid on the cycle immediately following end_of_str assertion
+ if (match_bus === 6'b000110) begin