xiiregexbuilder

commit 1a1bcf8e151fdcf339fd9373f6abddcf1df919f9
parent 86fef8c8666e67c87b876aa326d7f4e708a591af
Author: Vishrut Gurrala <maydayv7@gmail.com>
Date:   Tue,  7 Apr 2026 10:00:00 +0530

Week 3: Complete FPGA top wrapper and pin constraints (Part 3: Finalizing)

Diffstat:
M
output-eg/constraints.xdc
 | 
7
+++++++
M
output-eg/top_fpga.v
 | 
44
++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/output-eg/constraints.xdc b/output-eg/constraints.xdc
@@ -20,3 +20,10 @@ set_property IOSTANDARD LVCMOS33 [get_ports {match_leds[0]}]
 set_property PACKAGE_PIN K15 [get_ports {match_leds[1]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {match_leds[1]}]
 set_property PACKAGE_PIN J13 [get_ports {match_leds[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {match_leds[2]}]
+set_property PACKAGE_PIN N14 [get_ports {match_leds[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {match_leds[3]}]
+set_property PACKAGE_PIN R18 [get_ports {match_leds[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {match_leds[4]}]
+set_property PACKAGE_PIN V17 [get_ports {match_leds[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {match_leds[5]}]
diff --git a/output-eg/top_fpga.v b/output-eg/top_fpga.v
@@ -296,3 +296,47 @@ module top_fpga #(
                 S_EOL_END: begin
                     nfa_en <= 1'b1;
                     state  <= S_EOL_MATCH;
+                end
+
+                S_EOL_MATCH: begin
+                    nfa_en         <= 1'b1;
+                    nfa_end_of_str <= 1'b0;
+                    state          <= S_EOL_LATCH;
+                end
+
+                S_EOL_LATCH: begin
+                    snap_match <= match_bus;
+                    snap_bytes <= byte_count;
+                    match_leds <= match_bus;
+                    for (k = 0; k < 6; k = k + 1)
+                        if (match_bus[k]) match_count[k] <= match_count[k] + 16'd1;
+                    state <= S_TX_ARM;
+                end
+
+                S_TX_ARM: begin
+                    build_response(snap_match, snap_bytes);
+                    tx_send <= 1'b1;
+                    state   <= S_TX_WAIT;
+                end
+
+                S_TX_WAIT:
+                    if (tx_state == TX_IDLE && !tx_send) state <= S_RESET_NFA;
+
+                S_RESET_NFA: begin
+                    nfa_start <= 1'b1;
+                    nfa_en    <= 1'b1;
+                    state     <= S_IDLE;
+                end
+
+                S_QUERY_TX: begin
+                    build_response(6'b0, byte_count);
+                    tx_send <= 1'b1;
+                    state   <= S_TX_WAIT;
+                end
+
+                default: state <= S_IDLE;
+            endcase
+        end
+    end
+
+endmodule