xiiregexbuilder

FPGA-Accelerated Regular Expression Matching Engine
commit 0353a880c810bf5fb33dd5633bb11a14f488ecec
parent 042756fa5985d38096c916cc5219f6e64a847ed9
Author: RahulSannapureddy <rahul.sannapureddy@gmail.com>
Date:   Sun,  5 Apr 2026 07:54:46 +0530

Week 3: Extend simulation waveform traces (Part 2: Core logic)

Diffstat:
Mdump.vcd | 174+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 174 insertions(+), 0 deletions(-)

diff --git a/dump.vcd b/dump.vcd @@ -428,3 +428,177 @@ b10 > #170000 0! +0( + +#175000 +1! +1( +b0 / +b0 2 +b100 8 +b0 9 +b0 ; + +#180000 +0! +1% +0( +1, + +#185000 +1! +b100 ' +1( +14 +b0 8 + +#190000 +0! +0% +0( +0, + +#195000 +1! +b0 ' +1( +04 + +#200000 +0! +1$ +0( +1+ + +#205000 +1! +1( +b1 / +b10 0 +b1 2 +b10 3 +b1 5 +b1 8 +b10 9 +b1 ; +b10 < +b1 > + +#210000 +0! +0$ +0( +0+ + +#215000 +1! +1( +b10 / +b0 0 +b10 2 +b0 3 +b10 5 +b10 8 +b100 9 +b10 ; +b0 < +b10 > + +#220000 +0! +b1100010 & +0( +b1100010 - +b100 3 +b100 6 +b100 < +b100 ? + +#225000 +1! +1( +b0 / +b100 2 +b100 5 +b100 8 +b1000 9 +b100 ; +b0 < +b100 > + +#230000 +0! +1% +0( +1, + +#235000 +1! +b100 ' +1( +14 +b1000 8 +b0 9 +b0 ; + +#240000 +0! +0% +0( +0, + +#245000 +1! +b0 ' +1( +04 +b0 8 + +#250000 +0! +1$ +0( +1+ + +#255000 +1! +1( +b1 / +b100 0 +b1 2 +b0 3 +b1 5 +b1 8 +b1 ; +b1 > + +#260000 +0! +0$ +b1100001 & +0( +0+ +b1100001 - +b10 0 +b10 3 +b10 6 +b10 9 +b10 < +b10 ? + +#265000 +1! +1( +b10 / +b0 0 +b10 2 +b0 3 +b10 5 +b10 8 +b100 9 +b10 ; +b0 < +b10 > + +#270000 +0!