xiiregexbuilder, branch HEAD

Week 6: UART modules, example testbench, and repository configuration (Part 3: Finalizing)

2026-04-24T09:29:59Z

commit 3ad17970a37887e3110e5203d3ad0a741c345d88 parent 471ae799ee654084667d3635fd959ca9f4e0b452 Author: Vishrut Gurrala Date: Fri, 24 Apr 2026 14:59:59 +0530 Week 6: UART modules, example testbench, and repository configuration (Part 3: Finalizing)

Week 6: C++ compiler core updates, emitter logic, and PII FPGA wrapper (Part 3: Finalizing)

2026-04-24T02:17:08Z

commit 471ae799ee654084667d3635fd959ca9f4e0b452 parent 68de20aebb7b522651dd591789127470eaeaeefc Author: Achuthan TM Date: Fri, 24 Apr 2026 07:47:08 +0530 Week 6: C++ compiler core updates, emitter logic, and PII FPGA wrapper (Part 3: Finalizing)

Week 6: UART modules, example testbench, and repository configuration (Part 2: Core logic)

2026-04-23T19:04:17Z

commit 68de20aebb7b522651dd591789127470eaeaeefc parent 9fb3f273ed339b048202b5ea54b7a03a8f900964 Author: Vishrut Gurrala Date: Fri, 24 Apr 2026 00:34:17 +0530 Week 6: UART modules, example testbench, and repository configuration (Part 2: Core logic)

Week 6: C++ compiler core updates, emitter logic, and PII FPGA wrapper (Part 2: Core logic)

2026-04-23T11:51:25Z

commit 9fb3f273ed339b048202b5ea54b7a03a8f900964 parent 9741d4d3bc2f88f84a674202d63f15008f1cd2b0 Author: Achuthan TM Date: Thu, 23 Apr 2026 17:21:25 +0530 Week 6: C++ compiler core updates, emitter logic, and PII FPGA wrapper (Part 2: Core logic)

Week 6: PII guard top-level testbench and constraints (Part 3: Finalizing)

2026-04-23T04:38:34Z

commit 9741d4d3bc2f88f84a674202d63f15008f1cd2b0 parent 856f6b7b5f181faa34d3647ba0e1a7c714eba4d1 Author: Pranav Prabhu Kumble Date: Thu, 23 Apr 2026 10:08:34 +0530 Week 6: PII guard top-level testbench and constraints (Part 3: Finalizing)

Week 6: Verilog NFA generation for example regexes and project specifications (Part 3: Finalizing)

2026-04-22T21:25:42Z

commit 856f6b7b5f181faa34d3647ba0e1a7c714eba4d1 parent 95ad58a8359cbd2ad7cb090aba50c641410c0418 Author: yash modi Date: Thu, 23 Apr 2026 02:55:42 +0530 Week 6: Verilog NFA generation for example regexes and project specifications (Part 3: Finalizing)

Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 3: Finalizing)

2026-04-22T14:12:51Z

commit 95ad58a8359cbd2ad7cb090aba50c641410c0418 parent 10295686a022feddee6768c9b2a04d20e4e8d9c0 Author: RahulSannapureddy Date: Wed, 22 Apr 2026 19:42:51 +0530 Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 3: Finalizing)

Week 6: UART modules, example testbench, and repository configuration (Part 1: Initial definitions)

2026-04-22T06:59:59Z

commit 10295686a022feddee6768c9b2a04d20e4e8d9c0 parent c72154b995239edb5f06e280d9db90b8f9ed6087 Author: Vishrut Gurrala Date: Wed, 22 Apr 2026 12:29:59 +0530 Week 6: UART modules, example testbench, and repository configuration (Part 1: Initial definitions)

Week 6: Verilog NFA generation for example regexes and project specifications (Part 2: Core logic)

2026-04-21T23:47:08Z

commit c72154b995239edb5f06e280d9db90b8f9ed6087 parent ce33559706c8ba674c609821d7a40417efd668fe Author: yash modi Date: Wed, 22 Apr 2026 05:17:08 +0530 Week 6: Verilog NFA generation for example regexes and project specifications (Part 2: Core logic)

Week 6: PII guard top-level testbench and constraints (Part 2: Core logic)

2026-04-21T16:34:17Z

commit ce33559706c8ba674c609821d7a40417efd668fe parent 00a6e7e9cc488d819501b4b28ea01745faa0ba77 Author: Pranav Prabhu Kumble Date: Tue, 21 Apr 2026 22:04:17 +0530 Week 6: PII guard top-level testbench and constraints (Part 2: Core logic)

Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 2: Core logic)

2026-04-21T09:21:25Z

commit 00a6e7e9cc488d819501b4b28ea01745faa0ba77 parent 8232199844c35a09ed2bde578493b4a0d7fd42c6 Author: RahulSannapureddy Date: Tue, 21 Apr 2026 14:51:25 +0530 Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 2: Core logic)

Week 6: C++ compiler core updates, emitter logic, and PII FPGA wrapper (Part 1: Initial definitions)

2026-04-21T02:08:34Z

commit 8232199844c35a09ed2bde578493b4a0d7fd42c6 parent 54395ca613879057685a6b1cbc42ab4679da05d4 Author: Achuthan TM Date: Tue, 21 Apr 2026 07:38:34 +0530 Week 6: C++ compiler core updates, emitter logic, and PII FPGA wrapper (Part 1: Initial definitions)

Week 6: Verilog NFA generation for example regexes and project specifications (Part 1: Initial definitions)

2026-04-20T18:55:42Z

commit 54395ca613879057685a6b1cbc42ab4679da05d4 parent 0619ab7bb78d77d88c6f56969f6e2f187b137383 Author: yash modi Date: Tue, 21 Apr 2026 00:25:42 +0530 Week 6: Verilog NFA generation for example regexes and project specifications (Part 1: Initial definitions)

Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 1: Initial definitions)

2026-04-20T11:42:51Z

commit 0619ab7bb78d77d88c6f56969f6e2f187b137383 parent 33f6a42c6705eda20ec587eaf00c520288d4c08c Author: RahulSannapureddy Date: Mon, 20 Apr 2026 17:12:51 +0530 Week 6: PII guard documentation, TUI enhancements, and legacy cleanup (Part 1: Initial definitions)

Week 6: PII guard top-level testbench and constraints (Part 1: Initial definitions)

2026-04-20T04:30:00Z

commit 33f6a42c6705eda20ec587eaf00c520288d4c08c parent e4e352a8a144e54b5a12b961d025aa270a6daba8 Author: Pranav Prabhu Kumble Date: Mon, 20 Apr 2026 10:00:00 +0530 Week 6: PII guard top-level testbench and constraints (Part 1: Initial definitions)

Week 5: Peripheral integration, testbenches and simulation inputs (Part 3: Finalizing)

2026-04-19T13:00:00Z

commit e4e352a8a144e54b5a12b961d025aa270a6daba8 parent 18530b5463446ce65ca3c26acd1aa15243b99892 Author: RahulSannapureddy Date: Sun, 19 Apr 2026 18:30:00 +0530 Week 5: Peripheral integration, testbenches and simulation inputs (Part 3: Finalizing)

Week 5: Automated verilog emitter and assembler scripts (Part 3: Finalizing)

2026-04-19T00:23:34Z

commit 18530b5463446ce65ca3c26acd1aa15243b99892 parent d6f80a26c6a3c81784374ae7ed8576c1b605d8cd Author: Pranav Prabhu Kumble Date: Sun, 19 Apr 2026 05:53:34 +0530 Week 5: Automated verilog emitter and assembler scripts (Part 3: Finalizing)

Week 5: Peripheral integration, testbenches and simulation inputs (Part 2: Core logic)

2026-04-18T11:47:08Z

commit d6f80a26c6a3c81784374ae7ed8576c1b605d8cd parent 903e9453615b27acd18c33bcd86b5ea8d0c1f9f9 Author: RahulSannapureddy Date: Sat, 18 Apr 2026 17:17:08 +0530 Week 5: Peripheral integration, testbenches and simulation inputs (Part 2: Core logic)

Week 5: UART design and serial interface TUI implementation (Part 3: Finalizing)

2026-04-17T23:10:42Z

commit 903e9453615b27acd18c33bcd86b5ea8d0c1f9f9 parent cbded02aedf4957109c7f201ebb9d5037adfa90c Author: Vishrut Gurrala Date: Sat, 18 Apr 2026 04:40:42 +0530 Week 5: UART design and serial interface TUI implementation (Part 3: Finalizing)

Week 5: System-level integration and top level FPGA logic (Part 3: Finalizing)

2026-04-17T10:34:17Z

commit cbded02aedf4957109c7f201ebb9d5037adfa90c parent be54305005bc30221f60242bcc81993b9a281c48 Author: Achuthan TM Date: Fri, 17 Apr 2026 16:04:17 +0530 Week 5: System-level integration and top level FPGA logic (Part 3: Finalizing)

Week 5: UART design and serial interface TUI implementation (Part 2: Core logic)

2026-04-16T21:57:51Z

commit be54305005bc30221f60242bcc81993b9a281c48 parent efe089a5906c5f47f66a5f59bf2a7d4f21919827 Author: Vishrut Gurrala Date: Fri, 17 Apr 2026 03:27:51 +0530 Week 5: UART design and serial interface TUI implementation (Part 2: Core logic)

Week 5: Automated verilog emitter and assembler scripts (Part 2: Core logic)

2026-04-16T09:21:25Z

commit efe089a5906c5f47f66a5f59bf2a7d4f21919827 parent cca559debcc0dcaa6d085a67bbbe67cafd708fa2 Author: Pranav Prabhu Kumble Date: Thu, 16 Apr 2026 14:51:25 +0530 Week 5: Automated verilog emitter and assembler scripts (Part 2: Core logic)

Week 5: UART design and serial interface TUI implementation (Part 1: Initial definitions)

2026-04-15T20:45:00Z

commit cca559debcc0dcaa6d085a67bbbe67cafd708fa2 parent d7157f9d379865386434dbe183e39938726d6f41 Author: Vishrut Gurrala Date: Thu, 16 Apr 2026 02:15:00 +0530 Week 5: UART design and serial interface TUI implementation (Part 1: Initial definitions)

Week 5: Automated verilog emitter and assembler scripts (Part 1: Initial definitions)

2026-04-15T08:08:34Z

commit d7157f9d379865386434dbe183e39938726d6f41 parent b5cba03ff61bd34e091a58174d878f79f534c3f3 Author: Pranav Prabhu Kumble Date: Wed, 15 Apr 2026 13:38:34 +0530 Week 5: Automated verilog emitter and assembler scripts (Part 1: Initial definitions)

Week 5: Core processor logic and parallel engine implementation (Part 3: Finalizing)

2026-04-14T19:32:08Z

commit b5cba03ff61bd34e091a58174d878f79f534c3f3 parent 1638294121a88383f75e7e8c206f35f2e796a553 Author: yash modi Date: Wed, 15 Apr 2026 01:02:08 +0530 Week 5: Core processor logic and parallel engine implementation (Part 3: Finalizing)

Week 5: System-level integration and top level FPGA logic (Part 2: Core logic)

2026-04-14T06:55:42Z

commit 1638294121a88383f75e7e8c206f35f2e796a553 parent db8fb4edf3854d38715e2052d42f57c6ccaacff9 Author: Achuthan TM Date: Tue, 14 Apr 2026 12:25:42 +0530 Week 5: System-level integration and top level FPGA logic (Part 2: Core logic)

Week 5: Core processor logic and parallel engine implementation (Part 2: Core logic)

2026-04-13T18:19:17Z

commit db8fb4edf3854d38715e2052d42f57c6ccaacff9 parent 6bde5feec6bac8e253cb94ca9521b486037a80c3 Author: yash modi Date: Mon, 13 Apr 2026 23:49:17 +0530 Week 5: Core processor logic and parallel engine implementation (Part 2: Core logic)

Week 5: Peripheral integration, testbenches and simulation inputs (Part 1: Initial definitions)

2026-04-13T05:42:51Z

commit 6bde5feec6bac8e253cb94ca9521b486037a80c3 parent ab3a8165709ec9a9b3bbc77346401619672d8c06 Author: RahulSannapureddy Date: Mon, 13 Apr 2026 11:12:51 +0530 Week 5: Peripheral integration, testbenches and simulation inputs (Part 1: Initial definitions)

Week 5: System-level integration and top level FPGA logic (Part 1: Initial definitions)

2026-04-12T17:06:25Z

commit ab3a8165709ec9a9b3bbc77346401619672d8c06 parent c622612af22a288f67797d3efd77db0bd1594dc5 Author: Achuthan TM Date: Sun, 12 Apr 2026 22:36:25 +0530 Week 5: System-level integration and top level FPGA logic (Part 1: Initial definitions)

Week 5: Core processor logic and parallel engine implementation (Part 1: Initial definitions)

2026-04-12T04:30:00Z

commit c622612af22a288f67797d3efd77db0bd1594dc5 parent 7ce00ce8fe35c9aea464761be50a601e144d1615 Author: yash modi Date: Sun, 12 Apr 2026 10:00:00 +0530 Week 5: Core processor logic and parallel engine implementation (Part 1: Initial definitions)

Week 4: Python Interactive TUI, FPGA Program Scripts, and final verification traces (Part 3: Finalizing)

2026-04-10T04:30:00Z

commit 7ce00ce8fe35c9aea464761be50a601e144d1615 parent b1f236bf6138d253c98fb9013a4c7fa20ad9dff2 Author: Vishrut Gurrala Date: Fri, 10 Apr 2026 10:00:00 +0530 Week 4: Python Interactive TUI, FPGA Program Scripts, and final verification traces (Part 3: Finalizing)

Week 4: Python Interactive TUI, FPGA Program Scripts, and final verification traces (Part 2: Core logic)

2026-04-09T22:30:00Z

commit b1f236bf6138d253c98fb9013a4c7fa20ad9dff2 parent f87bd32015d5f293ce41b5f63d0de69b6805414b Author: Vishrut Gurrala Date: Fri, 10 Apr 2026 04:00:00 +0530 Week 4: Python Interactive TUI, FPGA Program Scripts, and final verification traces (Part 2: Core logic)

Week 4: Python Interactive TUI, FPGA Program Scripts, and final verification traces (Part 1: Initial definitions)

2026-04-09T16:30:00Z

commit f87bd32015d5f293ce41b5f63d0de69b6805414b parent f402b6ca0c8cb2ab86e3152f91e1e9e67cf7fc48 Author: Vishrut Gurrala Date: Thu, 9 Apr 2026 22:00:00 +0530 Week 4: Python Interactive TUI, FPGA Program Scripts, and final verification traces (Part 1: Initial definitions)

Week 4: Emitter optimization simulation verification traces (Part 3: Finalizing)

2026-04-09T10:30:00Z

commit f402b6ca0c8cb2ab86e3152f91e1e9e67cf7fc48 parent d6c34c118cad55b182f2398bc451bea15ba31a95 Author: yash modi Date: Thu, 9 Apr 2026 16:00:00 +0530 Week 4: Emitter optimization simulation verification traces (Part 3: Finalizing)

Week 4: Emitter optimization simulation verification traces (Part 2: Core logic)

2026-04-09T04:30:00Z

commit d6c34c118cad55b182f2398bc451bea15ba31a95 parent ac3d5d2f57af85a033baa5ca267312fbdb26b7c7 Author: yash modi Date: Thu, 9 Apr 2026 10:00:00 +0530 Week 4: Emitter optimization simulation verification traces (Part 2: Core logic)

Week 4: Emitter optimization simulation verification traces (Part 1: Initial definitions)

2026-04-08T22:30:00Z

commit ac3d5d2f57af85a033baa5ca267312fbdb26b7c7 parent 48a66bfc500eef570ceebbc96de93a37d04adcf0 Author: yash modi Date: Thu, 9 Apr 2026 04:00:00 +0530 Week 4: Emitter optimization simulation verification traces (Part 1: Initial definitions)

Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 3: Finalizing)

2026-04-08T16:30:00Z

commit 48a66bfc500eef570ceebbc96de93a37d04adcf0 parent c636ad41973ea81ab3b19a920d273e9607e54421 Author: Achuthan TM Date: Wed, 8 Apr 2026 22:00:00 +0530 Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 3: Finalizing)

Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 2: Core logic)

2026-04-08T10:30:00Z

commit c636ad41973ea81ab3b19a920d273e9607e54421 parent 545d26fe1baa8ea075838df67f4e6faad57deb99 Author: Achuthan TM Date: Wed, 8 Apr 2026 16:00:00 +0530 Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 2: Core logic)

Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 1: Initial definitions)

2026-04-08T04:30:00Z

commit 545d26fe1baa8ea075838df67f4e6faad57deb99 parent 1a1bcf8e151fdcf339fd9373f6abddcf1df919f9 Author: Achuthan TM Date: Wed, 8 Apr 2026 10:00:00 +0530 Week 4: Final NFA modules, Vivado synthesis scripts, timing closure traces (Part 1: Initial definitions)

Week 3: Complete FPGA top wrapper and pin constraints (Part 3: Finalizing)

2026-04-07T04:30:00Z

commit 1a1bcf8e151fdcf339fd9373f6abddcf1df919f9 parent 86fef8c8666e67c87b876aa326d7f4e708a591af Author: Vishrut Gurrala Date: Tue, 7 Apr 2026 10:00:00 +0530 Week 3: Complete FPGA top wrapper and pin constraints (Part 3: Finalizing)

Week 3: Full hardware verification simulation traces (Part 3: Finalizing)

2026-04-06T22:14:20Z

commit 86fef8c8666e67c87b876aa326d7f4e708a591af parent b30c53a6930f47da584b261dadf3291ed63f4bcb Author: Pranav Prabhu Kumble Date: Tue, 7 Apr 2026 03:44:20 +0530 Week 3: Full hardware verification simulation traces (Part 3: Finalizing)

Week 3: Complete FPGA top wrapper and pin constraints (Part 2: Core logic)

2026-04-06T15:58:41Z

commit b30c53a6930f47da584b261dadf3291ed63f4bcb parent d1b99d1b6e876814a909ca047abe1eff3daddd37 Author: Vishrut Gurrala Date: Mon, 6 Apr 2026 21:28:41 +0530 Week 3: Complete FPGA top wrapper and pin constraints (Part 2: Core logic)

Week 3: Full hardware verification simulation traces (Part 2: Core logic)

2026-04-06T09:43:02Z

commit d1b99d1b6e876814a909ca047abe1eff3daddd37 parent 4b3f38e1350bacc56bb8910fa29785a0a77df3d2 Author: Pranav Prabhu Kumble Date: Mon, 6 Apr 2026 15:13:02 +0530 Week 3: Full hardware verification simulation traces (Part 2: Core logic)

Week 3: Complete FPGA top wrapper and pin constraints (Part 1: Initial definitions)

2026-04-06T03:27:23Z

commit 4b3f38e1350bacc56bb8910fa29785a0a77df3d2 parent 89aad7f8fe7a89f038f0d28e4f20d0d39c0bcf19 Author: Vishrut Gurrala Date: Mon, 6 Apr 2026 08:57:23 +0530 Week 3: Complete FPGA top wrapper and pin constraints (Part 1: Initial definitions)

Week 3: Full hardware verification simulation traces (Part 1: Initial definitions)

2026-04-05T21:11:44Z

commit 89aad7f8fe7a89f038f0d28e4f20d0d39c0bcf19 parent 89d79be69ad02a0e9f5a249e9fc93f5a2738dfec Author: Pranav Prabhu Kumble Date: Mon, 6 Apr 2026 02:41:44 +0530 Week 3: Full hardware verification simulation traces (Part 1: Initial definitions)

Week 3: Extend simulation waveform traces (Part 3: Finalizing)

2026-04-05T14:56:05Z

commit 89d79be69ad02a0e9f5a249e9fc93f5a2738dfec parent e92ed1cba89830230f45d2f0afe7aa7c32cdeb58 Author: RahulSannapureddy Date: Sun, 5 Apr 2026 20:26:05 +0530 Week 3: Extend simulation waveform traces (Part 3: Finalizing)

Week 3: Implement UART RX and partial FPGA top wrapper (Part 3: Finalizing)

2026-04-05T08:40:26Z

commit e92ed1cba89830230f45d2f0afe7aa7c32cdeb58 parent 0353a880c810bf5fb33dd5633bb11a14f488ecec Author: Vishrut Gurrala Date: Sun, 5 Apr 2026 14:10:26 +0530 Week 3: Implement UART RX and partial FPGA top wrapper (Part 3: Finalizing)

Week 3: Extend simulation waveform traces (Part 2: Core logic)

2026-04-05T02:24:46Z

commit 0353a880c810bf5fb33dd5633bb11a14f488ecec parent 042756fa5985d38096c916cc5219f6e64a847ed9 Author: RahulSannapureddy Date: Sun, 5 Apr 2026 07:54:46 +0530 Week 3: Extend simulation waveform traces (Part 2: Core logic)

Week 3: Implement UART RX and partial FPGA top wrapper (Part 2: Core logic)

2026-04-04T20:09:07Z

commit 042756fa5985d38096c916cc5219f6e64a847ed9 parent bfe7a9821ad84be824769d432b5375d0e83ae22e Author: Vishrut Gurrala Date: Sun, 5 Apr 2026 01:39:07 +0530 Week 3: Implement UART RX and partial FPGA top wrapper (Part 2: Core logic)

Week 3: Extend simulation waveform traces (Part 1: Initial definitions)

2026-04-04T13:53:28Z

commit bfe7a9821ad84be824769d432b5375d0e83ae22e parent bde1d28d910545d40a9e617f7d6ef81148310252 Author: RahulSannapureddy Date: Sat, 4 Apr 2026 19:23:28 +0530 Week 3: Extend simulation waveform traces (Part 1: Initial definitions)

Week 3: Generate first batch of NFA Verilog modules (Part 3: Finalizing)

2026-04-04T07:37:49Z

commit bde1d28d910545d40a9e617f7d6ef81148310252 parent 887ac8bc533aee3cda032754c0f8222599f2ef6a Author: Achuthan TM Date: Sat, 4 Apr 2026 13:07:49 +0530 Week 3: Generate first batch of NFA Verilog modules (Part 3: Finalizing)

Week 3: Implement Top Testbench and start simulation logging (Part 3: Finalizing)

2026-04-04T01:22:10Z

commit 887ac8bc533aee3cda032754c0f8222599f2ef6a parent 4dec5d9a87d7091515b0a75301dd83e04977e9b5 Author: RahulSannapureddy Date: Sat, 4 Apr 2026 06:52:10 +0530 Week 3: Implement Top Testbench and start simulation logging (Part 3: Finalizing)

Week 3: Implement UART RX and partial FPGA top wrapper (Part 1: Initial definitions)

2026-04-03T19:06:31Z

commit 4dec5d9a87d7091515b0a75301dd83e04977e9b5 parent 03a26fc143c8feacc365a73952f3201de6cfd8be Author: Vishrut Gurrala Date: Sat, 4 Apr 2026 00:36:31 +0530 Week 3: Implement UART RX and partial FPGA top wrapper (Part 1: Initial definitions)

Week 3: Implement Top Testbench and start simulation logging (Part 2: Core logic)

2026-04-03T12:50:52Z

commit 03a26fc143c8feacc365a73952f3201de6cfd8be parent 1afac9076b61391997f852de92a74d1fb2e9e75b Author: RahulSannapureddy Date: Fri, 3 Apr 2026 18:20:52 +0530 Week 3: Implement Top Testbench and start simulation logging (Part 2: Core logic)

Week 3: Initial Verilog top wrapper and UART TX (Part 3: Finalizing)

2026-04-03T06:35:13Z

commit 1afac9076b61391997f852de92a74d1fb2e9e75b parent be037ac565931db31a2ec30e4e8376a364fe7c24 Author: Vishrut Gurrala Date: Fri, 3 Apr 2026 12:05:13 +0530 Week 3: Initial Verilog top wrapper and UART TX (Part 3: Finalizing)

Week 3: Generate first batch of NFA Verilog modules (Part 2: Core logic)

2026-04-03T00:19:33Z

commit be037ac565931db31a2ec30e4e8376a364fe7c24 parent 586ee1dc397750bfdc9014fa5902015ee4cf2e4a Author: Achuthan TM Date: Fri, 3 Apr 2026 05:49:33 +0530 Week 3: Generate first batch of NFA Verilog modules (Part 2: Core logic)

Week 3: Implement UART RX hardware FIFO (Part 3: Finalizing)

2026-04-02T18:03:54Z

commit 586ee1dc397750bfdc9014fa5902015ee4cf2e4a parent abc269ec4be88de2485c8ef07ca7e78a50fb3448 Author: yash modi Date: Thu, 2 Apr 2026 23:33:54 +0530 Week 3: Implement UART RX hardware FIFO (Part 3: Finalizing)

Week 3: Generate first batch of NFA Verilog modules (Part 1: Initial definitions)

2026-04-02T11:48:15Z

commit abc269ec4be88de2485c8ef07ca7e78a50fb3448 parent a40c44015b4f5a32571357cff412dde8766ac468 Author: Achuthan TM Date: Thu, 2 Apr 2026 17:18:15 +0530 Week 3: Generate first batch of NFA Verilog modules (Part 1: Initial definitions)

Week 3: Implement UART RX hardware FIFO (Part 2: Core logic)

2026-04-02T05:32:36Z

commit a40c44015b4f5a32571357cff412dde8766ac468 parent b58127612186e2684a3aa3cb4ebc4574c9926a8c Author: yash modi Date: Thu, 2 Apr 2026 11:02:36 +0530 Week 3: Implement UART RX hardware FIFO (Part 2: Core logic)

Week 3: Initial Verilog top wrapper and UART TX (Part 2: Core logic)

2026-04-01T23:16:57Z

commit b58127612186e2684a3aa3cb4ebc4574c9926a8c parent 9d8c9e9dc3de9037f4c6ac2a2c88f8763f4a91c3 Author: Vishrut Gurrala Date: Thu, 2 Apr 2026 04:46:57 +0530 Week 3: Initial Verilog top wrapper and UART TX (Part 2: Core logic)

Week 3: Implement UART RX hardware FIFO (Part 1: Initial definitions)

2026-04-01T17:01:18Z

commit 9d8c9e9dc3de9037f4c6ac2a2c88f8763f4a91c3 parent 4c9186bea3d96f16ab5d8a72d78eb026a8834f94 Author: yash modi Date: Wed, 1 Apr 2026 22:31:18 +0530 Week 3: Implement UART RX hardware FIFO (Part 1: Initial definitions)

Week 3: Initial Verilog top wrapper and UART TX (Part 1: Initial definitions)

2026-04-01T10:45:39Z

commit 4c9186bea3d96f16ab5d8a72d78eb026a8834f94 parent 251a9fc87ded97179ef42802e59bea5a992d1352 Author: Vishrut Gurrala Date: Wed, 1 Apr 2026 16:15:39 +0530 Week 3: Initial Verilog top wrapper and UART TX (Part 1: Initial definitions)

Week 3: Implement Top Testbench and start simulation logging (Part 1: Initial definitions)

2026-04-01T04:30:00Z

commit 251a9fc87ded97179ef42802e59bea5a992d1352 parent 3bc50cb168985a7a7599fd9983ef1956e0c829c8 Author: RahulSannapureddy Date: Wed, 1 Apr 2026 10:00:00 +0530 Week 3: Implement Top Testbench and start simulation logging (Part 1: Initial definitions)

Week 2: Add parser testing utility (Part 3: Finalizing)

2026-03-31T04:29:59Z

commit 3bc50cb168985a7a7599fd9983ef1956e0c829c8 parent 19c4f1dea715e4e3d43732b20043d53ef87e7443 Author: Pranav Prabhu Kumble Date: Tue, 31 Mar 2026 09:59:59 +0530 Week 2: Add parser testing utility (Part 3: Finalizing)

Week 2: Complete Verilog Emitter Optimization (Part 3: Finalizing)

2026-03-30T23:53:04Z

commit 19c4f1dea715e4e3d43732b20043d53ef87e7443 parent b37fdb4f722532ac3630160ba9fc41fdea36e368 Author: yash modi Date: Tue, 31 Mar 2026 05:23:04 +0530 Week 2: Complete Verilog Emitter Optimization (Part 3: Finalizing)

Week 2: Implement AST Parser (Part 3: Finalizing)

2026-03-30T19:16:09Z

commit b37fdb4f722532ac3630160ba9fc41fdea36e368 parent 491dc5bb2a0e3001b1a2f55203861697610ce06e Author: Pranav Prabhu Kumble Date: Tue, 31 Mar 2026 00:46:09 +0530 Week 2: Implement AST Parser (Part 3: Finalizing)

Week 2: Complete Verilog Emitter Optimization (Part 2: Core logic)

2026-03-30T14:39:13Z

commit 491dc5bb2a0e3001b1a2f55203861697610ce06e parent ed65d13844d6a6ee1e30c0378e87b9eca18effb7 Author: yash modi Date: Mon, 30 Mar 2026 20:09:13 +0530 Week 2: Complete Verilog Emitter Optimization (Part 2: Core logic)

Week 2: Add parser testing utility (Part 2: Core logic)

2026-03-30T10:02:18Z

commit ed65d13844d6a6ee1e30c0378e87b9eca18effb7 parent e61f0c4cb1f16d469d7c21c58ac1c967dc7a69a8 Author: Pranav Prabhu Kumble Date: Mon, 30 Mar 2026 15:32:18 +0530 Week 2: Add parser testing utility (Part 2: Core logic)

Week 2: Add Makefile for build automation (Part 3: Finalizing)

2026-03-30T05:25:23Z

commit e61f0c4cb1f16d469d7c21c58ac1c967dc7a69a8 parent cb0d9aba0f8b2d5d8f2a43d17c2eb32c51ef9fa3 Author: RahulSannapureddy Date: Mon, 30 Mar 2026 10:55:23 +0530 Week 2: Add Makefile for build automation (Part 3: Finalizing)

Week 2: Implement Lexer (Part 3: Finalizing)

2026-03-30T00:48:27Z

commit cb0d9aba0f8b2d5d8f2a43d17c2eb32c51ef9fa3 parent bf711fbd4dcf55b2101e316cafd3ef55f89adfb2 Author: Pranav Prabhu Kumble Date: Mon, 30 Mar 2026 06:18:27 +0530 Week 2: Implement Lexer (Part 3: Finalizing)

Week 2: Integrate compiler passes in main (Part 3: Finalizing)

2026-03-29T20:11:32Z

commit bf711fbd4dcf55b2101e316cafd3ef55f89adfb2 parent 1fcbf19350c8294cd19982d8b50360baf64633f2 Author: Achuthan TM Date: Mon, 30 Mar 2026 01:41:32 +0530 Week 2: Integrate compiler passes in main (Part 3: Finalizing)

Week 2: Implement AST Parser (Part 2: Core logic)

2026-03-29T15:34:36Z

commit 1fcbf19350c8294cd19982d8b50360baf64633f2 parent 907199802749d357c7f9a12bdb596fee78e5f6a7 Author: Pranav Prabhu Kumble Date: Sun, 29 Mar 2026 21:04:36 +0530 Week 2: Implement AST Parser (Part 2: Core logic)

Week 2: Complete Verilog Emitter Optimization (Part 1: Initial definitions)

2026-03-29T10:57:41Z

commit 907199802749d357c7f9a12bdb596fee78e5f6a7 parent a9386b4caec8fcf9c2b7545e2be8b251cdf1af26 Author: yash modi Date: Sun, 29 Mar 2026 16:27:41 +0530 Week 2: Complete Verilog Emitter Optimization (Part 1: Initial definitions)

Week 2: Add Makefile for build automation (Part 2: Core logic)

2026-03-29T06:20:46Z

commit a9386b4caec8fcf9c2b7545e2be8b251cdf1af26 parent f49928c22a00c08d06453648856f90d4d2abf537 Author: RahulSannapureddy Date: Sun, 29 Mar 2026 11:50:46 +0530 Week 2: Add Makefile for build automation (Part 2: Core logic)

Week 2: Implement Glushkov NFA Builder (Part 3: Finalizing)

2026-03-29T01:43:50Z

commit f49928c22a00c08d06453648856f90d4d2abf537 parent 6f7343019c63029335be0494abf485190a017509 Author: Achuthan TM Date: Sun, 29 Mar 2026 07:13:50 +0530 Week 2: Implement Glushkov NFA Builder (Part 3: Finalizing)

Week 2: Add Makefile for build automation (Part 1: Initial definitions)

2026-03-28T21:06:55Z

commit 6f7343019c63029335be0494abf485190a017509 parent 70d02833208fe275a03393cecca099a66bc8b080 Author: RahulSannapureddy Date: Sun, 29 Mar 2026 02:36:55 +0530 Week 2: Add Makefile for build automation (Part 1: Initial definitions)

Week 2: Begin Verilog Emitter Implementation (Part 3: Finalizing)

2026-03-28T16:29:59Z

commit 70d02833208fe275a03393cecca099a66bc8b080 parent 71535acc3c401f82ef63d68900a5930a2d7df7ea Author: yash modi Date: Sat, 28 Mar 2026 21:59:59 +0530 Week 2: Begin Verilog Emitter Implementation (Part 3: Finalizing)

Week 2: Implement Lexer (Part 2: Core logic)

2026-03-28T11:53:04Z

commit 71535acc3c401f82ef63d68900a5930a2d7df7ea parent 536594803c76145b84c19d51bc4362546e9a7bba Author: Pranav Prabhu Kumble Date: Sat, 28 Mar 2026 17:23:04 +0530 Week 2: Implement Lexer (Part 2: Core logic)

Week 2: Implement Glushkov NFA Builder (Part 2: Core logic)

2026-03-28T07:16:09Z

commit 536594803c76145b84c19d51bc4362546e9a7bba parent 0d2faab2f0211afadd26a9350ed5aa2b1ba3c0d1 Author: Achuthan TM Date: Sat, 28 Mar 2026 12:46:09 +0530 Week 2: Implement Glushkov NFA Builder (Part 2: Core logic)

Week 2: Begin Verilog Emitter Implementation (Part 2: Core logic)

2026-03-28T02:39:13Z

commit 0d2faab2f0211afadd26a9350ed5aa2b1ba3c0d1 parent ac8796a476323808a396dddd700772bcab5f504c Author: yash modi Date: Sat, 28 Mar 2026 08:09:13 +0530 Week 2: Begin Verilog Emitter Implementation (Part 2: Core logic)

Week 2: Implement AST Parser (Part 1: Initial definitions)

2026-03-27T22:02:18Z

commit ac8796a476323808a396dddd700772bcab5f504c parent af09500cd291b011c9b2790673508cb204643dd9 Author: Pranav Prabhu Kumble Date: Sat, 28 Mar 2026 03:32:18 +0530 Week 2: Implement AST Parser (Part 1: Initial definitions)

Week 2: Integrate compiler passes in main (Part 2: Core logic)

2026-03-27T17:25:23Z

commit af09500cd291b011c9b2790673508cb204643dd9 parent dac6d100b8256a2659a88ee42642452c90e07530 Author: Achuthan TM Date: Fri, 27 Mar 2026 22:55:23 +0530 Week 2: Integrate compiler passes in main (Part 2: Core logic)

Week 2: Add golden C++ reference regex engine (Part 3: Finalizing)

2026-03-27T12:48:27Z

commit dac6d100b8256a2659a88ee42642452c90e07530 parent 1314233eebd8a0f48ee7c9fbc7bde5d03499ffbd Author: RahulSannapureddy Date: Fri, 27 Mar 2026 18:18:27 +0530 Week 2: Add golden C++ reference regex engine (Part 3: Finalizing)

Week 2: Implement Glushkov NFA Builder (Part 1: Initial definitions)

2026-03-27T08:11:32Z

commit 1314233eebd8a0f48ee7c9fbc7bde5d03499ffbd parent 67bde232f6840495b986c67fdc1cb629471e7803 Author: Achuthan TM Date: Fri, 27 Mar 2026 13:41:32 +0530 Week 2: Implement Glushkov NFA Builder (Part 1: Initial definitions)

Week 2: Add golden C++ reference regex engine (Part 2: Core logic)

2026-03-27T03:34:36Z

commit 67bde232f6840495b986c67fdc1cb629471e7803 parent e298cda282f22b28115114d4c1aabc3c0b2572fb Author: RahulSannapureddy Date: Fri, 27 Mar 2026 09:04:36 +0530 Week 2: Add golden C++ reference regex engine (Part 2: Core logic)

Week 2: Add parser testing utility (Part 1: Initial definitions)

2026-03-26T22:57:41Z

commit e298cda282f22b28115114d4c1aabc3c0b2572fb parent b98cdd2ed1a02ffcd879c0abad800b27a10d02bd Author: Pranav Prabhu Kumble Date: Fri, 27 Mar 2026 04:27:41 +0530 Week 2: Add parser testing utility (Part 1: Initial definitions)

Week 2: Begin Verilog Emitter Implementation (Part 1: Initial definitions)

2026-03-26T18:20:46Z

commit b98cdd2ed1a02ffcd879c0abad800b27a10d02bd parent 9639da9d4aebf625f01e8b3987447850881bf3c4 Author: yash modi Date: Thu, 26 Mar 2026 23:50:46 +0530 Week 2: Begin Verilog Emitter Implementation (Part 1: Initial definitions)

Week 2: Add golden C++ reference regex engine (Part 1: Initial definitions)

2026-03-26T13:43:50Z

commit 9639da9d4aebf625f01e8b3987447850881bf3c4 parent 88f2f9885887916d3d699c62abc091396341bdec Author: RahulSannapureddy Date: Thu, 26 Mar 2026 19:13:50 +0530 Week 2: Add golden C++ reference regex engine (Part 1: Initial definitions)

Week 2: Implement Lexer (Part 1: Initial definitions)

2026-03-26T09:06:55Z

commit 88f2f9885887916d3d699c62abc091396341bdec parent e7faebb6ba14f20418524dd98261081bffad9d60 Author: Pranav Prabhu Kumble Date: Thu, 26 Mar 2026 14:36:55 +0530 Week 2: Implement Lexer (Part 1: Initial definitions)

Week 2: Integrate compiler passes in main (Part 1: Initial definitions)

2026-03-26T04:30:00Z

commit e7faebb6ba14f20418524dd98261081bffad9d60 parent 93a0cc14179bd8a2756f5fd49b25358d299940ff Author: Achuthan TM Date: Thu, 26 Mar 2026 10:00:00 +0530 Week 2: Integrate compiler passes in main (Part 1: Initial definitions)

Week 1: Add initial test inputs and regex patterns (Part 3: Finalizing)

2026-03-25T04:30:00Z

commit 93a0cc14179bd8a2756f5fd49b25358d299940ff parent 2d11fa4297c9b11fd5c88ec446e477698cd9e0c7 Author: RahulSannapureddy Date: Wed, 25 Mar 2026 10:00:00 +0530 Week 1: Add initial test inputs and regex patterns (Part 3: Finalizing)

Week 1: Add initial test inputs and regex patterns (Part 2: Core logic)

2026-03-25T01:04:17Z

commit 2d11fa4297c9b11fd5c88ec446e477698cd9e0c7 parent bfaeb9092479d42a4388c7cebf633ba571e0af7c Author: RahulSannapureddy Date: Wed, 25 Mar 2026 06:34:17 +0530 Week 1: Add initial test inputs and regex patterns (Part 2: Core logic)

Week 1: Add README and Use cases (Part 3: Finalizing)

2026-03-24T21:38:34Z

commit bfaeb9092479d42a4388c7cebf633ba571e0af7c parent 4218bc760e95ebe88b461025f964d168d9e34efa Author: Vishrut Gurrala Date: Wed, 25 Mar 2026 03:08:34 +0530 Week 1: Add README and Use cases (Part 3: Finalizing)

Week 1: Add gitignore and detailed architecture docs (Part 3: Finalizing)

2026-03-24T18:12:51Z

commit 4218bc760e95ebe88b461025f964d168d9e34efa parent 3aaf0d4787e0ccdd4ace8176bdb762f29fd014fc Author: Achuthan TM Date: Tue, 24 Mar 2026 23:42:51 +0530 Week 1: Add gitignore and detailed architecture docs (Part 3: Finalizing)

Week 1: Add README and Use cases (Part 2: Core logic)

2026-03-24T14:47:08Z

commit 3aaf0d4787e0ccdd4ace8176bdb762f29fd014fc parent f4f8ccdf923532ea7e9a579c6ad460a33c6fc08c Author: Vishrut Gurrala Date: Tue, 24 Mar 2026 20:17:08 +0530 Week 1: Add README and Use cases (Part 2: Core logic)

Week 1: Define Verilog Emitter headers (Part 3: Finalizing)

2026-03-24T11:21:25Z

commit f4f8ccdf923532ea7e9a579c6ad460a33c6fc08c parent a2fa577fb0c3bb5a176b4668f71d69a28eb2cc2b Author: yash modi Date: Tue, 24 Mar 2026 16:51:25 +0530 Week 1: Define Verilog Emitter headers (Part 3: Finalizing)

Week 1: Add System Specifications (Part 3: Finalizing)

2026-03-24T07:55:42Z

commit a2fa577fb0c3bb5a176b4668f71d69a28eb2cc2b parent 51a64e9e0dfe25c9eb116a39a1364e21e0996635 Author: Pranav Prabhu Kumble Date: Tue, 24 Mar 2026 13:25:42 +0530 Week 1: Add System Specifications (Part 3: Finalizing)

Week 1: Add initial test inputs and regex patterns (Part 1: Initial definitions)

2026-03-24T04:30:00Z

commit 51a64e9e0dfe25c9eb116a39a1364e21e0996635 parent 2296e98334fb70f3982baf354471684a12b83ae2 Author: RahulSannapureddy Date: Tue, 24 Mar 2026 10:00:00 +0530 Week 1: Add initial test inputs and regex patterns (Part 1: Initial definitions)

Week 1: Add README and Use cases (Part 1: Initial definitions)

2026-03-24T01:04:17Z

commit 2296e98334fb70f3982baf354471684a12b83ae2 parent 03632b820298e2fbe967e1a85518b4e3563342e6 Author: Vishrut Gurrala Date: Tue, 24 Mar 2026 06:34:17 +0530 Week 1: Add README and Use cases (Part 1: Initial definitions)

Week 1: Add gitignore and detailed architecture docs (Part 2: Core logic)

2026-03-23T21:38:34Z

commit 03632b820298e2fbe967e1a85518b4e3563342e6 parent 7ed9849ed122a34e2a44bb3e34c3b217d8f78b41 Author: Achuthan TM Date: Tue, 24 Mar 2026 03:08:34 +0530 Week 1: Add gitignore and detailed architecture docs (Part 2: Core logic)